Sony CMT-LX10R / HCD-LX10R Service Manual ▷ View online
HCD-LX10R
33
Pin No.
Pin Name
I/O
Description
60
MS
I
Micro controller interface mode selection signal input terminal Fixed at “H” in this set
61
DOUT
O
Digital audio data output terminal Not used
62
AOUT1
O
Audio data output terminal Not used
63
BCKO
O
Bit clock signal output terminal
64
LRCKO
O
L/R sampling clock signal output terminal Not used
65
AIN
I
Digital audio data input terminal
66
BCKI
I
Bit clock signal input terminal
67
LRCKI
I
L/R sampling clock signal input terminal
68
VDD1
-
Power supply terminal (+1.5V)
69
VSS1
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFO
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCO
O
EFM slice level output terminal
81
RFI
I
RF signal input terminal
82
RFRPI
I
RF ripple signal input terminal
83
RFEQO
O
EFM slice level output terminal
84
VRO
O
Reference voltage (+1.65V) output terminal
85
RESIN
O
External resistor connection terminal
86
VMDIR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCI
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFO
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3V)
91
LDO
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
92
MDI
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
C
I
Main beam (C) input from the optical pick-up block
95
A
I
Main beam (A) input from the optical pick-up block
96
D
I
Main beam (D) input from the optical pick-up block
97
B
I
Main beam (B) input from the optical pick-up block
98
F
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
E
I
Sub beam (E) input from the optical pick-up block
HCD-LX10R
34
USB BOARD IC901 92CD28AFG-7AC9 (M (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
USB-RST
I
Reset signal input from the system controller “L”: reset
2
I-USB-DI
I
Ready to send signal input from the system controller
3, 4
INT1, INT2
O
Not used
5
INT3
I
Function selection signal input terminal Fixed at “H” in this set
6
DVCC3B
-
Power supply terminal (+3.1 V)
7 to 9
XT1, XT2, PWE
-
Not used
10
DVSS1B
-
Ground terminal
11
DVCC1B
-
Power supply terminal Not used
12
RVOUT1
O
Reference voltage (+3.1 V) output terminal Not used
13, 14
RVIN
I
Reference voltage (+3.1 V) input terminal
15
RVOUT2
O
Reference voltage (+3.1 V) output terminal Not used
16
DVCC1A
-
Power supply terminal Not used
17
DVSS1A
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC
-
Power supply terminal (+3.1 V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC3A
-
Power supply terminal (+3.1 V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0-U to BUS3-U
O
Serial data output to the CD-MP3 processor
59
BUCK-U
O
Serial data transfer clock signal output to the CD-MP3 processor
60
CCE-U
O
Chip enable signal output to the CD-MP3 processor
61
A23
O
Not used
62
DVSS
-
Ground terminal
63
DVCC3A
-
Power supply terminal (+3.1 V)
64
RD
O
Output enable signal output to the S-RAM
65
SRWR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
TA0IN
O
Not used
69
BOOT
I
Boot mode selection signal input terminal “L”: boot mode
70
SRAM-CS
O
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input terminal Fixed at “H” in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC3A
-
Power supply terminal (+3.1 V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB VBUS power on/off control signal output terminal “H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal Fixed at “H” in this set
82
X1USB
O
Not used
83
DVSS
-
Ground terminal
84
O-USB-DO
O
Clear to send signal output to the system controller
85
DATA
I
Audio data input from the CD-MP3 processor
86
CLK
I
Audio data transfer clock signal input from CD-MP3 processor
87
O-USB-SO
O
Serial data output to the system controller
88
I-USB-SI
I
Serial data input from the system controller
89
SPCLK
-
Not used
90
SO0
-
Not used
91
SI0
-
Not used
92
BCK
O
Bit clock signal output to the CD-MP3 processor
93
A-IN
O
Audio data output to the CD-MP3 processor
HCD-LX10R
35
Pin No.
Pin Name
I/O
Description
94
GATE
O
Gate signal output to the CD-MP3 processor
95
DVCC3A
-
Power supply terminal (+3.1 V)
96
REQ-U
I
Request signal input from the CD-MP3 processor
97
ST-REQ
I
Request signal input from the CD-MP3 processor
98, 99
PG1, PG0
I
Function selection signal input terminal Fixed at “L” in this set
100
DVSS
-
Ground terminal
HCD-LX10R
36
PANEL BOARD IC502 MB90F831PF-G-SPE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
O-USBRESET/
DAB1.2V
O
Reset signal output to the USB controller
2
O-POWER
O
Main power on/off control signal output terminal “H”: main power on
3
O-AMP-ON
O
Output muting on/off signal output to the power amplifi er
4
O-CD/USM 3.3V ON
O
CD power on/off control signal output terminal “H”: CD power on
5
O-LED
O
LED drive signal output terminal for the LCD back light
6
I-RDS DS
I
RDS data input terminal Not used
7
I-TU-DO
I
Serial data input from the AM/FM DET
8
O-CD-LOAD OUT
O
Motor drive signal output terminal for the loading section
9
I-RMC
I
Remote control signal input from the remote control receiver
10
O-CD-LOAD IN
O
Motor drive signal output terminal for the loading section
11
O-FUNC SC
O
Serial data transfer clock signal output to the electrical volume
12
O-FUNC SD
O
Serial data output to the electrical volume
13
X0A
I
Sub system clock input terminal (32.768 kHz)
14
X1A
O
Sub system clock output terminal (32.768 kHz)
15
VCC
-
Power supply terminal (+3.1V)
16
VSS
-
Ground terminal
17 to 20
BUS0 to BUS3
O
Serial data output to the CD-MP3 processor
21
O-IPOD POWER
O
VBUS power supply on/off control signal output terminal Not used
22
O-LED-STBY
O
LED drive signal output terminal for STANDBY indicator
23
O-CD-DR MUTE
O
Motor drive on/off control signal output to the motor/coil driver
24
I-CD REQ
I
Request signal input from the CD-MP3 processor
25
O-CD BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
26
O-CD CCE
O
Chip enable signal output to the CD-MP3 processor
27
O-CD RESET
O
System reset signal output to the CD-MP3 processor “L”: reset
28
O-USB SEL/
DAB 3.3VSEL
O
Data selection signal output terminal
29
I-UXB TXD/DAB DO
I
Serial data input terminal
30
I-USB DO
I
Clear to send signal input from the USB controller
31
O-USB RXD/DAB DI
O
Serial data output terminal
32
AVCC
-
Power supply terminal (+3.2V)
33
I-IPOD TXD
I
Serial data input terminal Not used
34
O-USB DI
O
Ready to send signal output to the USB controller
35
AVSS
-
Ground terminal
36
I-P-MONI
I
Power monitor signal input terminal
37, 38
I-KEY_1, I-KEY_2
I
Front panel key input terminal (A/D input)
39
I-KEY_3
I
Destination setting terminal
40
I-SW CD CHECK/
OUT
I
Switch detection signal input terminal for loading section
41
I-KEY WAKE UP
I
Front panel key input terminal (A/D input) for the power key
42
I-HOLD
I
Hold signal input terminal
43
I-CD SBSY
I
Subcode block sync signal input from the CD-MP3 processor
44
VSS
-
Ground terminal
45
I-RDS SC
I
Serial data transfer clock signal input terminal Not used
46
I-TU ANSD
I
Auto gain control signal input terminal
47
O-IPOD-RXD
O
Serial data output terminal Not used
48
I-IPOD DETECT
I
iPod detection signal input terminal Not used
49
SEL USB-IPOD
O
Function selection signal output terminal Not used
50
SEL USB-WM/
I-MODEL
O
Function selection signal output terminal Not used
51 to 53
MD2 to MD0
-
Not used
54
RSTX
I
Reset signal input from the reset switch “L”: reset
55
O-TU-CE
O
Chip enable signal output to the AM/FM DET
56
O-TU-CLK
O
Serial data transfer clock signal output to the AM/FM DET
57
O-TU-DI
O
Serial data output to the AM/FM DET
58
VLCD
-
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive
voltage
voltage
59 to 62
COM0 - COM3
O
Common drive signal output to the liquid crystal display
63, 64
SEG0, SEG1
O
Segment drive signal output to the liquid crystal display
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