Sony CMT-L7HD / HCD-L7HD Service Manual ▷ View online
65
HCD-L7HD
• IC600 uPD703033AYGF-M46-3BA (CD Control) (CD Board)
I/O
O
O
I/O
—
I/O
—
O
O
—
—
O
O
O
O
I/O
—
O
I/O
O
O
—
O
O
O
—
O
O
O
O
O
O
I
I
—
—
—
I
—
—
O
I
I
I
I
—
O
O
O
O
O
—
Pin Name
DACDAT
DACCLK
IICDATA
—
IICCLK
—
DATA
CLK
EVDD
EVSS
PWM4
PWM1
XLT
LDON
SUBQ
—
SQCLK
SENSE
PWM2
PWM3
VPP
SPMUTE
X4
CTRL1
—
OMUTE
AMUTE
DMUTE
BDPWR
BDRST
DACRST
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
ENC1—4
ENC5
SW1
SW2
—
D.SENS.OUT
LOD1POS
LOD1NEG
LOD2POS
LOD2NEG
—
Description
DAC data output
DAC clock output
12C bus data input/output
Not used
12C bus clock input/output
Not used
Data output for CXD30689
Clock output for CXD30689
+5 V power terminal
Ground terminal
PWM4 (not used)
PWM1
Latch output for CXD30689
Laser power control output
SUBQ data input/output
Not used
SUBQ clock output
SENSE input/output
PWM2
PWM3
Internal connection/Power for writing to the flash ROM
Spindle motor muting output (not used)
4 times speed switching output (not used)
2 times speed switching output (Normal speed: H, 2 x speed: L) (not used)
Not used
Optical output muting output (not used)
Analog muting output (not used)
DAC muting output (not used)
BD power control output
BD reset output
DAC reset output (not used)
System reset input
Sub clock (not used)
Sub clock (not used)
Capacitor connection terminal for regulator
Main clock
Main clock
Ground terminal
+5 V power terminal
Clock output (not used)
Encoder input 1-4
Encoder input 5 (not used)
Chucking motor switch input
Loading motor switch input
Not used
D sensor output
Loading motor output (+)
Loading motor output (–)
Chucking motor output (+)
Chucking motor output (–)
Not used
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25-27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43-46
47
48
49
50
51
52
53
54
55
56,57
66
HCD-L7HD
Pin No.
58
59
60-67
68
69-73
74
75
76
77
78
79,80
81
82
83
84
85,86
87
88
89,90
91
92
93
94-96
97
98
99
100
I/O
—
—
—
O
—
—
—
I
I
I
—
I
I
I
I
—
I
I
I
I
—
I
—
O
I
O
O
Pin Name
BVDD
BVSS
—
CHECK
—
AVDD
AVSS
AVREF
OPTSNS1
OPTSNS2
—
SEL0
SEL1
SEL2
SEL3
—
MECHA—JIG
ADJ
IICHELP
SCOR
—
AC—CUT
—
—
—
—
DACLAT
Description
+5 V power terminal
Ground terminal
Not used
Check terminal
Not used
+5 V power terminal
Analog ground terminal
Analog reference voltage
D sensor input
L sensor input
Not used
Destination select input (Overseas: H, Japan: L)
Model select input (SL7: H, SL1: L) Fixing H
Model select input (not used) Fixing L
BD JIG select input (Normal: H, BD only: L) Fixing H
Not used
MECHA JIG (fixing L)
Adjustment mode input (fixing H)
1
2
C bus help input
CXD3068 SUBQ SYNC input
Not used
AC off input
Not used
Flash ROM data output
Flash ROM data input
Flash ROM clock output
DAC latch output
67
HCD-L7HD
I/O
—
I/O
—
I
I
—
I
O
—
I
—
I
—
I
—
I/O
—
I/O
—
I/O
I/O
O
I
I/O
O
O
I
—
O
I
—
I
—
I
—
I
—
—
—
—
—
I
—
I
—
I
I
—
—
Pin Name
NC
A1IN
NC
BYTE
CNVSS
NC
RESET
X-OUT
VSS
X-IN
VCC
NMI
NC
HD_P_DOWN
NC
IIC-HELP
NC
A1OUT
NC
IIC-CLK
IIC-DATA
TXD1
RXD1
CLK1
RTS1
TXD
RXD
NC
RTS
CTS
NC
PULLDOWN
NC
PULLUP
NC
NC
NC
VCC
NC
VSS
NC
HD DEV REC STT IN
NC
MODEL
AVSS
DEST
VREF
AVCC
NC
Description
Not used
ControlA1 II (not used)
Not used
GND (8bit DATA BUS)
GND (SingleChip MODE)
Not used
RESET (from STR)
Main clock
GND
Main clock
Vcc (3.3V)
NMI(pullup to VCC)
Not used
Notice power down from STR
Not used
IIC HELP
Not used
ControlA1 II(not used)
Not used
IIC CLK
IIC DATA
TXD (for FLASH writer)
RXD (for FLASH writer)
CLK(for FLASH writer)
RTS (for FLASH writer)
Transmit to HD (SH-3)
Receive from HD (SH-3)
Not used
Transmit to HD (SH-3)
Receive from HD (SH-3)
Not used
Pulldown to GND
Not used
Pullup to VCC
Not used
Pullup to VCC
Not used
Vcc (3.3V)
Not used
GND
Not used
HD DEV REC STT IN
Not used
Model select
GND (A/D power)
Destination select
GND (A/D reference)
Vcc (A/D power)
Not used
Pin No.
1-4
5
6,7
8
9
10,11
12
13
14
15
16
17
18,19
20
21,22
23
24,25
26
27,28
29
30
31
32
33
34
35
36
37
38
39
40
41
42-45
46
47-50
51
52-61
62
63
64
65-80
81
82-94
95
96
97
98
99
100
• IC1000 M30620MCN-A08FP (HDD Master) (HDD IF Board)
68
HCD-L7HD
I/O
I
—
O
I
—
I
I
I
I
I
I
O
O
O
I/O
O
O
—
O
—
O
I
I
O
O
—
O
—
O
O
I
—
I/O
—
I/O
—
I/O
—
I/O
O
—
O
—
O
—
O
—
O
—
Pin Name
MD1,2
VCC-RTC
XTAL2
EXTAL2
VSS-RTC
NMI
IRQ0 (CXD 1859A)
IRQ1 (IDE PRIMARY)
IRQ2 (IDE SECONDARY)
IRQ3
IRQ4(USB)
LINE MUTE
CD/XOPT
ADDA_RST
CTS
SLICER_SEL
SPDIF_SEL
VssQ
LOCK
VccQ
ADDA_MUTE
PTA7(MS LOAD IN)
PTA6(CAM IN)
PTA5(MTR R OUT)
PTA4(MTR F OUT)
Vss
PTA3(MS POWER)
Vcc
PTA2(WP)
PTA1(USB POWER)
PTA0(USB)
VssQ
D15
VccQ
D14-6
VssQ
D5
VccQ
D4-0
A0-3
VssQ
A4
VccQ
A5-13
VssQ
A14
VccQ
A15-21
Vss
Description
Clock mode setup input
Power supply terminal for RTC (1.8V)
RTC crystal oscillator terminal
RTC crystal oscillator terminal
Ground terminal for RTC
Request signal input for non-maskable interrupt
Interrupt request signal (CXD1859)
Interrupt request signal (IDE primary)
Interrupt request signal (IDE secondary)
Interrupt request signal (not used)
Interrupt request signal (USB) (not used)
LINE MUTE signal output (not used)
CD/optical input selection output
AD/DA reset output
CTS signal
Slicer selection signal output
SPDIF selection signal output (not used)
Ground terminal
LOCK signal output
Power supply terminal (3.3V)
AD/DA mute signal output
Detection signal of write data input (not used)
CAM signal input (not used)
Signal output ( R ) of loading motor drive (not used)
Signal output ( F ) of loading motor drive (not used)
Ground terminal
Control signal output of write data
Power supply terminal (1.8V)
Write protect signal output for FLASH ROM
Control signal output of USB power supply
USB VBUS signal input
Ground terminal
Data bus
Power supply terminal (3.3V)
Data bus
Ground terminal
Data bus
Power supply terminal (3.3V)
Data bus
Address bus
Ground terminal
Address bus
Power supply terminal (3.3V)
Address bus
Ground terminal
Address bus
Power supply terminal (3.3V)
Address bus
Ground terminal
Pin No.
1,2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-44
45
46
47
48-52
53-56
57
58
59
60-68
69
70
71
72-78
79
• IC101 HD6417709ABT100B (Master Control) (HDD SUB Board)
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