Sony CMT-L7HD / HCD-L7HD Service Manual ▷ View online
61
61
HCD-L7HD
6-29. Schematic Diagram – POWER Section –
62
62
HCD-L7HD
• IC Block Diagrams
• Waveforms
– BD Board –
– BD Board –
IC1362 SN74HC74ANS-E05
– TOUCH SW Board –
IC101 CXD3068Q
– BD Board –
IC103 CXA2581N-T4
CE
RFDC
ADIO
IGEN
ASYO
ASYI
RFAC
CLTV
FILO
FILI
PCO
BIAS
VCTL
V16M
VPCO
TE
ASYE
MD2
DOUT
DOUT
LRCK
PCMD
BCK
EMPH
XTSL
XTAI
XTAO
SOUT
SOCK
XOLT
SOCK
XOLT
SQSO
SQCK
SQCK
SCSY
SBSO
EXCK
EXCK
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
W
FCK
XUGF
XPCK
GFS
C2PO
SCOR
CAM
WDCK
COUT
MIRR
SE
FE
VC
FE
VC
TES1
TEST
TEST
FFDR
TRDR
TFDR
SRDR
SFDR
FSTO
SSTP
LOCK
PWMI
PWMI
FOK
FRDR
MDP
DFCT
CLOCK
GENERATOR
ASYMMETRY
CORRECTOR
CORRECTOR
DIGITAL
PLL
CPU
INTERFACE
INTERFACE
CORRECTOR
PROCESSOR
SUB CODE
RAM
32K
DEMODURATOR
EFM
ERROR
D/A
DIGITAL
OUT
INTERFACE
SERVO
INTERFACE
SERVO
AUTO
MIRR
DFCT
DFCT
FOK
SERVO
FOCUS
SERVO DSP
SERVO
SERVO
SLED
TRACKING
FOCUS PWM
GENERATOR
GENERATOR
GENERATOR
GENERATOR
SLED PWM
TRACKING PWM
A/D
CONVERTER
OPAMP
ANALOG SW
PWM GENERATOR
DIGITAL
CLV
SERVO BLOCK
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
–
+
–
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
RW/ROM
VC
RW/ROM
DVC
+
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
–
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
14
1
2 3
4
5
6
7
13 12 11
10
9
8
VCC
GND
CK
CLR
CK
CLR
Q
PR
Q
Q
PR
Q
D
D
1
IC101
us
(XTAO)
4.2 Vp-p
29.6 ns
2 V/DIV,10 ns/DIV
– AMP Board –
2
IC600
eh
(XT2)
3
IC600
ek
(X2)
3.9 Vp-p
50 ns
1 V/DIV,20 ns/DIV
1 V/DIV,10
µ
s/DIV
3.8 Vp-p
30.5
µ
s
4
IC300
4
5.1 Vp-p
20.3 ns
2 V/DIV,10 ns/DIV
– CD Board –
– MAIN Board –
5
IC745
2
6
IC500
eh
(XT2)
1 V/DIV,10
µ
s/DIV
1 V/DIV,20 ns/DIV
5 Vp-p
81.3 ns
7
IC500
ek
(X2)
3.4 Vp-p
50 ns
1 V/DIV,20 ns/DIV
3.3 Vp-p
30.5
µ
s
– FL Board –
8
Q1281 (Collector)
21.6 Vp-p
33.5
µ
s
10 V/DIV,20
µ
s/DIV
– HDD SUB Board –
9
X102 (IC101
<zbb>
(XTAL))
3.4 Vp-p
200 ns
1 V/DIV,100 ns/DIV
– HDD IF Board –
q;
IC1000
qd
(X-OUT)
qa
IC1002
qa
2.7Vp-p
22.2 ns
3.8 Vp-p
100 ns
1 V/DIV,10 ns/DIV
1 V/DIV,40 ns/DIV
qs
IC1100
wd
(XI)
qd
IC1101
wd
(XI)
2 V/DIV,40 ns/DIV
2 V/DIV,100 ns/DIV
5 Vp-p
166 ns
5.5 Vp-p
80 ns
63
HCD-L7HD
6-30. IC Pin Function Descriptions
• IC500 uPD703033AYGF-M45-3BA (Master Control) (MAIN Board)
I/O
O
O
I/O
O
I/O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
—
O
I
I
O
O
O
—
O
O
O
I
—
I
I
—
—
—
I
—
—
O
O
I
O
O
O
I
I
I
Pin Name
FL-DATA
FL-CLK
IIC DATA
FL-CE1
IIC CLK
FL_CE2
LED DRV DATA
LED DRV CLK
EVDD
EVSS
LED DRV STB
LED DRV CLR
FAN-ON
FAN-LOW
SM CS
SM DATA
SM CLK
SM PG MUTING
SM NSP MUTING
SM INIT
VPP
SM DRV IC RST
SM OPC
HP_IN
HP_MUTING
SPK-RELAY
AD-RESET
LINE MUTE
GEQ-DATA
GEQ-CLK
REC-MUTING
TAPE-IN
—
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
PLL-CLK
PLL-DI
PLL-DO
PLL-CE
ST-MUTING
STEREO
TUNED
RDS-DATA
Description
Data output for display
Clock output for display
IIC data input/output
Enable output for display
IIC clock output
Enable output for display
LED data output (not used)
LED clock output (not used)
+5 V power terminal
Ground terminal
LED strobe output (not used)
LED reset output (not used)
Fan motor ON/OFF output
Fan motor HIGH/LOW control output
S-MASTER latch output
S-MASTER data output
S-MASTER clock output
S-MASTER PG mute output (not used)
S-MASTER NSP mute output
S-MASTER initialize
Power output for writing flash ROM
S-MASTER driver IC reset output
S-MASTER OPC input
Headphones connected/not-connected input
Headphones mute output
Speaker relay output (not used)
ADC reset output
Not used
Data output for M61519FP
Clock output for M61519FP
REC OUT mute output (not used)
MD/TAPE connected/not-connected input
Not used
System reset input
SUB clock input
SUB clock output
Regulator output stabilizer capacitance is connected to this terminal.
Main clock output
Main clock input
Ground terminal
+5 V power terminal
Clock output (not used)
PLL clock output for tuner
PLL data input for tuner
PLL data output for tuner
PLL enable output for tuner
Mute output for tuner
Tuner STEREO detection input
Tuner tuning input
Tuner RDS data input (for AEP, UK destination)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
64
HCD-L7HD
Pin No.
51
52
53
54
55
56,57
58
59
60-63
64
65
66
67
68
69,70
71,72
73
74
75
76
77-79
80,81
82-84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
O
O
O
—
—
—
I
O
O
O
I
I
—
O
—
—
—
I
I
I
—
I
I
I
I
O
I
I
I
I
I
—
I
I
O
O
I/O
Pin Name
SOFT CHECK1
SOFT CHECK2
AM
DEVICE RESET OUT
DEVICE ACCUT OUT
—
BVDD
BVSS
DEST1-4
PWR-RELAY
DEVICE VDD
ON/STANDBY
JOG1 A
JOG1 B
—
LED1,2
LED3
AVDD
AVSS
AVREF
KEY1-3
REC LEVEL INPUT L,R
—
MODEL1
DEVICE1
DEVICE2
DEVICE3
FL-RST
KEY INIT
ACCUT
PCPON
RM INIT
SIRCS
—
RDS-CLK
SELF-WRITE-IN
SELF-WRITE-OUT
SELF-WRITE-CLK
IIC HELP
Description
Main operation check terminal
Power saving operation check terminal
Function AM output (for AEP, UK destination)
Reset output for HDD
AC off output
Not used
+5 V power terminal
Ground terminal
Destination setting terminal 1-4 (Refer to destination, model and device sheet.)
Power relay output (Clock display: H, Echo mode: L)
Device power control output
ON/STANDBY output
JOG 1A input
JOG 1B input
Not used
LED control output for illumination
Not used
+5 V power terminal
Ground terminal
Analog reference voltage
Key input 1-3
Reset level input L and R
Not used
Model setting
Device setting (DISPLAY)
Device setting (IO)
Device setting (CD)
Display reset output
Key interrupt input
AC off detection input
Power control input from a PC
Remote control interrupt input
Remote control input
Not used
Tuner RDS clock input (for AEP, UK destination)
Write data input to the flash ROM
Flash ROM data output
Flash ROM clock output
IIC help input/output
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