Sony CMT-G1BIP / CMT-G1IP / HCD-G1BIP / HCD-G1IP Service Manual ▷ View online
HCD-G1BiP/G1iP
49
IC107 IRS2052M
IC102 BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
6
VSS_OUT
7
V+
16 GND
11 CE0
12 CE1
9 INL
10 INR
3
VDD_OUT
8
V–
15 LATCH
1
OUTL
2
BOUTL
13 DATA
4
OUTR
5
BOUTR
14 CLOCK
+
–
–
+
–
–
LOSC
LOSC
BIAS
INTERFACE
&
LOGIC
HO2
NC
24
LO2
20
HO1
14
NC
13
VB2
22
CLIP1 46
COMP1 45
NC
NC 48
CSD 47
1
VAA 43
IN1 44
GND 41
OTW
2
NC
12
VS1
11
NC
10
NC
35
NC
36
VREF
34
OCSET
33
DT
32
VS2
26
NC
25
OTP
29
NC
28
NC
27
VB1
15
CSH1
16
VCC2
18
COM2
19
LO1
17
CLIP2 38
NC 37
COMP2 39
IN2 40
FAULT
3
CKO
4
X1B
5
X1A
6
X2B
7
X2A
8
XSL
9
PROTECTION
CONTROL
CLOCK
OSCILLATION
SOFT SHUTDOWN
CONTROL
GD
23
GD
GD
GD
UVBS1
UVBS2
OCH1
OCL1
OCL2
OCTS
UVAA
UVCC
CSH2
21
OCH2
+
–
+
–
OTA1
VSS 42
VCC
31
COM
30
OTA2
PWM
1
PWM
2
DEADTIME
2
REFERENCE
VOLTAGE
DEADTIME
1
OVER
TEMPERATURE
VCC
LOW SIDE SUB
– AMP Board –
IC101 NJW1159V (TE2)
HCD-G1BiP/G1iP
50
VREF
OSC
IBIAS
SLOPE
UNDER VOLTAGE
LOCK OUT
ERROR
AMP
DRIVE
LOGIC
LOGIC
S
R
PWM
THERMAL
SHUTDOWN
LVS
LVS
OVER CURRENT
PROTECT
VREG
VCC
SOFT
START
BST 1
VIN 2
SW 3
GND 4
EN
7
FB
5
COMP
6
SS
8
SEGMENT
DRIVER
GRID
DRIVER
CG-RAM
ADDRESS SELECTOR
DC-RAM
CG-ROM
8 BIT
SHIFT
REGISTER
TIMING
GENERATOR 2
TIMING
GENERATOR 1
COMMAND
DECODER
CONTROL
CIRCUIT
PORT
DRIVER
WRITE
ADDRESS
COUNTER
READ
ADDRESS
COUNTER
GR1
32
SG20
16
SG19
15
GR2
33
OSCI 50
VSS 49
VDD 56
RSTB 52
OSCO 51
AD-RAM
DUTY CONTROL
OSCILLATOR
DIGIT CONTROL
CLKB 54
DIN 55
CSB 53
P1 57
P2 58
P2 58
AD
DRIVER
AD2 59
AD1 60
AD1 60
SG4 64
SG3 63
SG2 62
SG1 61
SG35
31
SG34
30
SG33
29
SG32
28
SG31
27
SG30
26
SG29
25
SG28
24
SG27
23
SG26
22
SG25
21
SG24
20
SG23
19
SG22
18
SG21
17
SG18
14
SG17
13
SG16
12
SG15
11
SG14
10
SG13
9
SG12
8
SG1
1
7
SG10
6
SG9
5
SG8
4
SG7
3
SG6
2
SG5
1
GR3
34
GR4
35
GR5
36
GR6
37
GR7
38
GR8
39
GR9
40
GR10
41
GR1
1
42
GR12
43
GR13
44
GR14
45
GR15
46
GR16
47
VEE
48
– FL Board –
IC4101 PT6302LQ-010
– DCDC Board –
IC951 – 953 BD9329AEFJ-E2
HCD-G1BiP/G1iP
51
• IC Pin Function Description
BD94D BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
AVSS3
-
Ground terminal
2
RFZI
I
RF ripple zero crossing signal input terminal
3
RFRP
O
RF ripple signal output terminal
4
SBAD
O
Sub beam addition signal output terminal Not used
5
FEO
O
Focus error signal output terminal Not used
6
TEO
O
Tracking error signal output terminal
7
TEZI
I
Tracking error zero crossing signal input terminal
8
AVDD3
-
Power supply terminal (+3.3V)
9
FOO
O
Focus coil drive signal output terminal
10
TRO
O
Tracking coil drive signal output terminal
11
VREF
I
Reference voltage (+1.65V) input terminal
12
FMO
O
Sled motor drive signal output terminal
13
DMO
O
Spindle motor drive signal output terminal
14
VSSP3
-
Ground terminal
15
VCOI
I
VCO control voltage input terminal
16
VDDP3
-
Power supply terminal (+3.3V)
17
VDD1
-
Power supply terminal (+1.5V)
18
VSS1
-
Ground terminal
19
FGIN
I
FG signal input terminal Not used
20
IN_SW
I
Disc inner position detection signal input terminal Not used
21
/DFCT
O
Not used
22
XVSS3
-
Ground terminal
23
XI
I
System clock input terminal (16.9344 MHz)
24
XO
O
System clock output terminal (16.9344 MHz)
25
XVDD3
-
Power supply terminal (+3.3V)
26
DVSS3
-
Ground terminal
27
ROUT
O
Audio data (R-ch) output terminal Not used
28
DVDD3
-
Power supply terminal (+3.3V)
29
DVR
O
Reference voltage (+1.65V) output terminal Not used
30
LOUT
O
Audio data (L-ch) output terminal Not used
31
DVSS3
-
Ground terminal
32
VDDT3
-
Power supply terminal (+3.3V)
33
VSS1
-
Ground terminal
34
VDD1
-
Power supply terminal (+1.5V)
35
VDDM1
-
Power supply terminal (+1.5V)
36
SRAMSTB
I
S-RAM standby mode control signal input terminal Fixed at “L” in this unit
37
XRST
I
Reset signal input from the system controller “L”: reset
38 to 41
BUS0 to BUS3
I
Serial data input from the system controller
42
BUCK
I
Serial data transfer clock signal input from the system controller
43
XCCE
I
Chip enable signal input from the system controller
44
TEST
I
Setting terminal for test mode Normally fi xed at “L”
45
IRQ
I
Interrupt request signal input terminal Not used
46
ST_REQ/CKO
O
Request signal output terminal Not used
47
AOUT2
O
Audio data output terminal Not used
48
REQ
O
Request signal output to the system controller
49
PIO1/ST_REQ
O
Request signal output terminal Not used
50
PIO2
O
Not used
51
GATE
I
Gate signal input terminal
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
FOK
O
Not used
56
IPF
O
Not used
57
/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal Not used
59
GPIN
I
Not used
HCD-G1BiP/G1iP
52
Pin No.
Pin Name
I/O
Description
60
MS
I
Micro controller interface mode selection signal input terminal Fixed at “H” in this unit
61
DOUT
O
Digital audio data output terminal Not used
62
AOUT1
O
Audio data output to the DSP
63
BCKO
O
Bit clock signal output to the DSP
64
LRCKO
O
L/R sampling clock signal output to the DSP
65
AIN
I
Digital audio data input terminal Not used
66
BCKI
I
Bit clock signal input terminal Not used
67
LRCKI
I
L/R sampling clock signal input terminal Not used
68
VDD1
-
Power supply terminal (+1.5V)
69
VSS1
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFO
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCO
O
EFM slice level output terminal
81
RFI
I
RF signal input terminal
82
RFRPI
I
RF ripple signal input terminal
83
RFEQ0
O
EFM slice level output terminal
84
VRO
O
Reference voltage (+1.65V) output terminal
85
RESIN
O
External resistor connection terminal
86
VMDIR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCI
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFO
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3V)
91
LDO
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
92
MDI
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
C
I
Main beam (C) input from the optical pick-up block
95
A
I
Main beam (A) input from the optical pick-up block
96
D
I
Main beam (D) input from the optical pick-up block
97
B
I
Main beam (B) input from the optical pick-up block
98
F
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
E
I
Sub beam (E) input from the optical pick-up block
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