Sony CMT-EH45DAB / HCD-EH45DAB Service Manual ▷ View online
HCD-EH45DAB
21
Pin No.
Pin Name
I/O
Description
1
AVSS3
-
Ground terminal
2
RFZi
I
RF ripple zero crossing signal input terminal
3
RFRP
O
RF ripple signal output terminal
4
SBAD/RFDC
O
Sub beam addition signal or RF peak detection signal output terminal Not used
5
FEi
O
Focus error signal output terminal Not used
6
TEi
O
Tracking error signal output terminal
7
TEZi
I
Tracking error zero crossing signal input terminal
8
AVDD3
-
Power supply terminal (+3.3 V)
9
FOo
O
Focus coil drive signal output terminal
10
TRo
O
Tracking coil drive signal output terminal
11
VREF
I
Reference voltage (+1.65V) input terminal
12
FMo
O
Sled motor drive signal output terminal
13
DMo
O
Spindle motor drive signal output terminal
14
VSSP3
-
Ground terminal
15
VCOi
I
VCO control voltage input terminal
16
VDDP3
-
Power supply terminal (+3.3 V)
17
VDD1
-
Power supply terminal (+1.5 V)
18
VSS
-
Ground terminal
19
FGiN
I
FG signal input terminal Not used
20
IO0 (/HSO)
I
Disc inner position detection signal input terminal
21
IO1 (/UHSO)
O
Not used
22
XVSS3
-
Ground terminal
23
XI
I
System clock input terminal (16.9344 MHz)
24
XO
O
System clock output terminal (16.9344 MHz)
25
XVDD3
-
Power supply terminal (+3.3 V)
26
DVSS3
-
Ground terminal
27
RO
O
Audio data (R-ch) output to the input selector
28
DVDD3
-
Power supply terminal (+3.3 V)
29
DVR
O
Reference voltage (+1.65V) output terminal
30
LO
O
Audio data (L-ch) output to the input selector
31
DVSS3
-
Ground terminal
32
VDDT3
-
Power supply terminal (+3.3 V)
33
VSS1
-
Ground terminal
34
VDD1
-
Power supply terminal (+1.5 V)
35
VDDM1
-
Power supply terminal (+1.5 V)
36
SRAMSTB
I
S-RAM standby mode control signal input terminal Fixed at "L" in this set
37
XRST
I
Reset signal input from the system controller "L": reset
38, 39
BUS0, BUS1
I
Serial data input from the system controller
40
BUS2 (SO)
I
Serial data input from the system controller
41
BUS3 (SI)
I
Serial data input from the system controller
42
BUCK (CLK)
I
Serial data transfer clock signal input from the system controller
43
XCCE
I
Chip enable signal input from the system controller
44
TEST
I
Setting terminal for test mode Normally fi xed at "L"
45
IRQ
I
Interrupt request signal input terminal Not used
46
AoUT3 (PO4)
O
Request signal output terminal Not used
47
AoUT2 (PO5)
O
Audio data output terminal Not used
48
PIO0
O
Request signal output to the system controller
49, 50
PIO1, PIO2
O
Not used
51
PIO3
I
Gate signal input terminal Not used
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used
56
IPF
O
Not used
• IC Pin Function Description
CD BOARD IC101 (CD-MP3 PROCESSOR) TC94A70FG-006
CD BOARD IC101 (CD-MP3 PROCESSOR) TC94A70FG-006
HCD-EH45DAB
22
Pin No.
Pin Name
I/O
Description
57
SFSY/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal Not used
59
GPIN
I
Not used
60
MS
I
Microcomputer interface mode selection signal input terminal Fixed at "H" in this set
61
DOUT (PO6)
O
Digital audio data output terminal Not used
62
AOUT (PO7)
O
Audio data output terminal Not used
63
BCK (PO8)
O
Bit clock signal output terminal Not used
64
LRCK (PO9)
O
L/R sampling clock signal output terminal Not used
65
AIN (PI4)
I
Digital audio data input terminal Not used
66
BCKi (PI5)
I
Bit clock signal input terminal Not used
67
LRCKi (PI6)
I
L/R sampling clock signal input terminal Not used
68
VDD1
-
Power supply terminal (+1.5 V)
69
VSS
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3 V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFo
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCo
O
EFM slice level output terminal
81
RFi
I
RF signal input terminal
82
RFRPi
I
RF ripple signal input terminal
83
RFEQo
O
EFM slice level output terminal
84
VRo
O
Reference voltage (+1.65V) output terminal
85
RESiN
O
External resistor connection terminal
86
VMDiR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFo
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3 V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit
"H": laser diode on
"H": laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
96
FPi2 (D)
I
Main beam (D) input from the optical pick-up block
97
FPi1 (B)
I
Main beam (B) input from the optical pick-up block
98
TPi (F)
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
TNi (E)
I
Sub beam (E) input from the optical pick-up block
HCD-EH45DAB
23
• IC Pin Function Description
PANEL BOARD IC701 MB90F830PF-GE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
LED
O
LED drive signal output terminal for liquid crystal display back light "H": LED on
2
CD OPEN/CLOSE
I
CD lid open/close detection switch input terminal
"L": CD lid is closed, "H": CD lid is opened
"L": CD lid is closed, "H": CD lid is opened
3
REQ
I
Request signal input from the CD-MP3 processor
4
MMUT
O
Muting signal output to the coil/motor driver
5 to 8
BUS0 to BUS3
O
Serial data output to the CD-MP3 processor
9
RMC
I
Remote control signal input from the remote control receiver
10
BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
11
XCCEN
O
Chip enable signal output to the CD-MP3 processor
12
XRST
O
Reset signal output to the CD-MP3 processor "L": reset
13
X2
I
Sub system clock input terminal (32.768 kHz)
14
X3
O
Sub system clock output terminal (32.768 kHz)
15
VCC
-
Power supply terminal (+3.3V)
16
VSS
-
Ground terminal
17 to 21
NC
-
Not used
22
LED_STBY
O
LED drive signal output terminal for STANDBY indicator "L": LED on
23
CD_ON
O
Power supply on/off control signal output terminal for CD section "H": power on
24 to 26
NC
-
Not used
27
DAB_1.2V
O
Power supply (+1.2V) on/off control signal output terminal for DAB tuner module
"H": power on
"H": power on
28
DAB_3.3V
O
Power supply (+3.3V) on/off control signal output terminal for DAB tuner module
"H": power on
"H": power on
29
DAB_DI
O
Serial data output to the DAB tuner module
30
NC
-
Not used
31
DAB_DO
I
Serial data input from the DAB tuner module
32
AVCC
-
Power supply terminal (+3.3V)
33
FUNC_SDA
O
Serial data output to the electrical volume
34
AMP_ON
O
Standby control signal output to the power amplifi er "L": standby
35
AVSS
-
Ground terminal
36
P_MONI
I
Power monitor input terminal
37, 38
KEY1, KEY2
I
Front panel key input terminal (A/D input)
39
NC
-
Not used
40
TP_STATE
I
REC/PB detection signal input terminal "L": PB, "H": REC
41
KEY0
I
Power key input terminal
42
HOLD
I
Hold signal input terminal
43
SBSY
I
Subcode block sync signal input from the CD-MP3 processor
44
VSS
-
Ground terminal
45, 46
NC
-
Not used
47
SUFIX
I
Destination setting terminal Not used
48
RE_VOL
I
Jog dial pulse input from the rotary encoder (for VOLUME)
49, 50
NC
-
Not used
51
MD2
I
Mode setting terminal Fixed at "L" in this set
52, 53
MD1, MD0
I
Mode setting terminal Fixed at "H" in this set
54
RESET
I
Reset signal input terminal "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
55 to 57
NC
-
Not used
58
V3
-
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive volt-
age
age
59 to 62
COM0 to COM3
O
Common drive signal output to the liquid crystal display
63, 64
SEG0, SEG1
O
Segment drive signal output to the liquid crystal display
65
VCC
-
Power supply terminal (+3.3V)
66
VSS
-
Ground terminal
67 to 89
SEG2 to SEG24
O
Segment drive signal output to the liquid crystal display
90
VCC
-
Power supply terminal (+3.3V)
91
VSS
-
Ground terminal
HCD-EH45DAB
24
• IC Block Diagrams
– CD Board –
– CD Board –
IC201 TK63115SCL-G@GT
THERMAL &
OVER CURRENT
PROTECTION
VOLTAGE
REFERENCE
ON/OFF
CONTROL
VIN 1
GND 2
VCONT 3
NC
4
VOUT
5
+
–
1
2
3
4
5
6
7
8
9
10
11
12
13
13
14
28
27
26
24
23
22
21
20
19
18
17
16
15
25
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT-DOWN
REGULATOR
REGULATOR
BIAS TRAP
LEVEL
SHIFT
MUTE
LEVEL
SHIFT
D.BUFF
D.BUFF
D.BUFF
GND
IN4
IN4'
BIAS
VCC
VCC
IN3'
IN3
VO3(+)
VO3(–)
VO4(–)
VO4(+)
RESETt
OPIN
VO1(–)
REGB
VO1(+)
IN1
RESET
REGOUT
MUTE
GND
IN2'
IN2
VO2(+)
VO2(–)
GND
OPOUT
D.BUFF
D.BUFF
D.BUFF
D.BUFF
D.BUFF
REGULA
TOR
VCC
VCC
OUT1
VCC
OUT2
IN2
PRE GND
IN1
P.
P.
ST
ANDBY
2
FIL
TER
1
3
4
5
6
7
8
11
13
POWER GND
10
9
12
PRE
DRIVE AMP
INPUT
AMP
STANDBY
SWITCH
THERMAL
SHUT DOWN
PROTECTOR
POP NOISE
PREVENTION
CIRCUIT
REFERENCE
AMP
RIPPLE
FILTER
OUTPUT
AMP
PRE
DRIVE AMP
INPUT
AMP
OUTPUT
AMP
IC401 BA5826SFP-E2
– MAIN Board –
IC101 TK70540SCL-G
IC301 LA4631-E
Pin No.
Pin Name
I/O
Description
92
X1
O
Main system clock output terminal (5.53 MHz)
93
X0
I
Main system clock input terminal (5.53 MHz)
94 to 100
SEG25 to SEG31
O
Segment drive signal output to the liquid crystal display
OVER HEAT &
OVER CURRENT
PROTECTION
BANDGAP
REFERENCE
CONTROL
CIRCUIT
GND
VIN
2
5
VOUT
4
NP
3
VCONT
1
+
–
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