Sony CMT-CPZ3 / HCD-CPZ3 Service Manual ▷ View online
HCD-CPZ3
49
Pin No.
Pin Name
I/O
Description
57
A
I
A signal input from the optical pick-up block
58
B
I
B signal input from the optical pick-up block
59
C
I
C signal input from the optical pick-up block
60
D
I
D signal input from the optical pick-up block
61
AVDD4
-
Power supply terminal (+3.3V)
62
RFDCO
O
Not used
63
PDSENS
I
Not used
64
AC_SUM
O
RFAC summing ampli
fi er signal output terminal
65
EQ_IN
O
RF equalizer circuit input terminal
66
LD
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
67
PD
I
Light amount monitor input from the optical pick-up block laser diode
68
RFC
I
Equalizer cut off frequency adjustment terminal
69
AVSS4
-
Ground terminal
70
RFACO
O
EFM signal output terminal
71
RFACI
I
EFM signal input terminal
72
AVDD3
-
Power supply terminal (+3.3V)
73
BIAS
I
Asymmetry circuit constant current input terminal
74
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
75
ASYO
O
Playback EFM full-swing output terminal
76
VPCO
O
Charge pump output terminal for broad-band EFM PLL
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
AVSS3
-
Ground terminal
79
CLTV
I
VCO1 control voltage input terminal for multiplier
80
FILO
O
Filter output terminal for master PLL
81
FILI
I
Filter input terminal for master PLL
82
PCO
O
Charge pump output terminal for master PLL
83
SVSS
-
Ground terminal
84
SVDD
-
Power supply terminal (+2.5V)
85
SSTB-MP3
I
MP3 standby on/off control signal input terminal “L”: standby
86
VDD
-
Power supply terminal (+2.5V)
87
VSS
-
Ground terminal
88
TEST1
I
For test terminal Normally
fi xed at “L”
89
DATA
I
CD serial data input from the system controller
90
CLK2
I
MP3 serial data transfer clock signal input from the system controller
92
SVDD
-
Power supply terminal (+2.5V)
93
JTAGTCK
-
Not used
94
JTAGTDI
-
Not used
95
JTAGTDO
-
Not used
96
JTAGTMS
-
Not used
97
TRST
-
Not used
98
VSS
-
Ground terminal
99
VDD
-
Power supply terminal (+2.5V)
100
IOVDD2
-
Power supply terminal (+3.3V)
101
DOUT
O
Digital audio signal output
102
TEST
I
For test terminal Normally
fi xed at “L”
103
TES1
I
For test terminal Normally
fi xed at “L”
104
IOVSS2
-
Ground terminal
105
PLLVDD
-
Power supply terminal (+2.5V)
106
PLLVSS
-
Ground terminal
107
XVSS
-
Ground terminal
108
XTAO
O
System clock output terminal (16.9344 MHz)
109
XTAI
I
System clock input terminal (16.9344 MHz)
110
XVDD
-
Power supply terminal (+2.5V)
111
AVDD1
-
Power supply terminal (+3.3V)
112
AOUT1
O
L-ch analog audio signal output terminal
113
VREFL
O
L-ch reference voltage output terminal
114
AVSS1
-
Ground terminal
115
AVSS2
-
Ground terminal
116
VREFR
O
R-ch reference voltage output terminal
HCD-CPZ3
50
Pin No.
Pin Name
I/O
Description
117
AOUT2
O
R-ch analog audio signal output terminal
118
AVDD1
-
Power supply terminal (+3.3V)
119
IOVDD0
-
Power supply terminal (+3.3V)
120
IOVSS0
-
Ground terminal
HCD-CPZ3
51
MAIN BOARD IC301 M30624MGP-A41FPU0 (SYSTEM CONTROLLER) (Serial No. 5138501 or smaller)
IC301 M3062LFGPFP (SYSTEM CONTROLLER) (Serial No. 5138502 or larger)
Pin No.
Pin Name
I/O
Description
1
AC DET
I
Protect signal input terminal
2
ST MUTE
O
Tuner muting on/off control signal output terminal “H”: muting on
3
MP3 SSTB
O
MP3 standby on/off control signal output terminal “L”: standby
4
SIRCS
I
Remote control signal input terminal
5
MP3 DATA OUT
O
MP3 serial data output to the CD DSP
6
MP3 DATA IN
I
MP3 serial data input terminal
7
MP3-CLK
O
MP3 serial data transfer clock signal output to the CD DSP
8
BYTE
I
External data bus line byte selection signal input terminal fi xed at “L”
9
CNVSS
-
Processor mode switch terminal (for test)
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (10 MHz)
14
VSS
-
Ground terminal
15
XIN
I
Main system clock input terminal (10 MHz)
16
VCC
-
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Not used
18
RDS INT
I
Interrupt status input from the tuner (FM/AM)
19
CD SCOR
I
Sub-code sync (S0+S1) detection signal input from the CD DSP
20
AC CUT
I
AC detection signal input terminal “L” AC off
21
ST CLK
O
PLL serial data transfer clock signal output to the tuner (FM/AM)
22
ST DATA IN
I
PLL serial data input from the tuner (FM/AM)
23
ST DATA OUT
O
PLL serial data output to the tuner (FM/AM)
24
ST CE
O
PLL serial chip enable signal output to the tuner (FM/AM)
25
TUNED IN
I
Tuning detection signal input from the tuner (FM/AM)
26
RDS-DATA
I
Serial data input from the tuner (FM/AM)
27
TC TRIG
O
Trigger plunger on/off control signal output terminal “H”: plunger on
28
TC CAPM CNT1
O
TC capstan motor drive signal output terminal
29
IIC CLK
I/O IIC data reading clock signal input or transfer clock signal output terminal Not used
30
IIC DATA
I/O IIC two-way data bus terminal Not used
31
TC PLAY
I
Tape play detection switch input terminal (Serial No. 5138501 or smaller only)
“L”: tape play mode
32
BIAS ON/OFF
O
Recording bias on/off control signal output terminal “H”: bias on
33
TC PB/REC SW
O
Playback/record selection signal output terminal “L”: playback, “H”: record
34
TC LINE MUTE
O
Line muting on/off selection signal output to the HA12215F
35
CD DATA
O
CD serial data output to the CD DSP
36
CD SENS
I
SENS signal input from the CD DSP
37
CD CLK
I
CD serial data transfer clock signal input from the CD DSP
38
TC REC MUTE
O
Recording muting on/off control signal output terminal
39
ALC
O
Automatic limiter control signal output terminal
40
S-MASTER INIT
O
Initialize signal output to the stream processor
41
S-MASTER
NSP MUTE
O
NSP muting on/off signal output to the stream processor
42
S-MASTER LATCH
O
Serial data latch pulse signal output to the stream processor
43
S-MASTER SHIFT
O
Shift clock signal output to the stream processor
44
S-MASTER DATA
O
Serial data transfer output to the stream processor
45
S-MASTER SD
I
Shut down state input from the power driver “L”: shut down
46
S-MASTER RST
O
Reset signal output to the stream processor
47
S-MASTER
SOFT MUTE
O
Soft muting on/off control signal output to the stream processor
48
S-MASTER
PG MUTE
O
Reset signal output to the power driver
49
S-MASTER OVF
O
System reset signal output to the stream processor
50
AMP SC
O
Serial data transfer clock signal output to the electrical volume
51
AMP SI
O
Serial output to the electrical volume
52
LINE MUTE
O
Line muting on/off selection signal output terminal
53
HP MUTE
O
Headphone muting on/off selection signal output terminal
54
HP DET
I
Headphone detection signal input terminal “H”: headphone on
Ver. 1.1
HCD-CPZ3
52
Pin No.
Pin Name
I/O
Description
55
STEREO
I
FM stereo detection signal input from the tuner (FM/AM) “L”: stereo
56
LCD ON/OFF
O
LCD on/off control signal output terminal “H”: LCD on
57
LCD INH
O
Reset signal output to the LCD driver “L”: reset
58
LCD SCL
O
Signal output for discriminating between command and display data to the LCD driver
“L”: display data, “H”: command
“L”: display data, “H”: command
59
LCD DATA
O
Serial output to the LCD driver
60
LCD SCL
O
Serial data transfer clock signal output to the LCD driver
61
LCD CE
O
Chip enable signal output to the LCD driver
62
VCC
-
Power supply terminal (+3.3V)
63
SOFT TEST
I
For test terminal Normally: open
64
VSS
-
Ground terminal
65
LED TAPE
O
LED drive signal output terminal “H”: tape function
66
LED TUNER
O
LED drive signal output terminal “H”: tuner function
67
LED CD
O
LED drive signal output terminal “H”: CD function
68
VOLUME A
I
Jog dial pulse input from the rotary encoder for the VOLUME (A phase input)
69
VOLUME B
I
Jog dial pulse input from the rotary encoder for the VOLUME (B phase input)
70
FOLDER A
I
Jog dial pulse input from the rotary encoder (A phase input)
71
FOLDER B
I
Jog dial pulse input from the rotary encoder (B phase input)
72
LED STAND BY
O
LED drive signal output terminal “H”: standby
73
EEPROM-SDA
I/O
Two-way data bus terminal Not used
74
WAKE UP KEY
I
Key interruption processing start signal input terminal
75
EEPROM-SCL
O
Serial data transfer clock signal output terminal Not used
76
CDM SW2 (CLOSE)
I
Detection input from the chuck switch “L”: loading in
77
CDM SW1 (OPEN)
I
Detection input from the out switch “L”: loading out
78
CDM SW3
(TRIGGER)
I
Detection input terminal Not used
79
CDM LOAD OUT
O
CD loading motor control signal (eject direction) output terminal “H” active
80
CDM LOAD IN
O
CD loading motor control signal (loading direction) output terminal “H” active
81
CD POWER ON/OFF
O
CD power on/off control signal output terminal “H”: power on
82
CD XTACN
O
Oscillation circuit on/off switch control signal output to the CD DSP
“L”: oscillation stop, “H”: self-oscillation
“L”: oscillation stop, “H”: self-oscillation
83
CD XRST
O
Reset signal output to the CD DSP “L”: reset
84
MP3 IREQ
O
MP3 data request signal output to the CD DSP
85
MP3 XLAT
O
MP3 serial data latch pulse output to the CD DSP
86
MP3 REQ
O
MP3 chip select signal output to the CD DSP
87
MP3 ACK
O
MP3 acknowledge signal output to the CD DSP
88
CD XLAT
O
CD serial data latch pulse output to the CD DSP
89
TREBLE
I
Jog dial pulse input from the rotary encoder for the treble
90
BASS
I
Jog dial pulse input from the rotary encoder for the bass
91
TC END SW
I
Tape end detect sensor input terminal “H” input when the tape end detected
92
TC HALF/REC SW
I
Cassette in and recording direction detection signal input terminal
“L”: side B recording, center voltage: cassette in (stop), “H”: side A recording
“L”: side B recording, center voltage: cassette in (stop), “H”: side A recording
93
SPEC IN
I
Destination setting terminal
94, 95
KEY2, KEY1
I
Key input (A/D input) terminal for the front panel
96
AVSS
-
Ground terminal
97
KEY0
I
Key input (A/D input) terminal for the front panel
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVCC
-
Power supply terminal (+3.3V)
100
POWER RELAY
ON/OFF
O
Main power on/off relay drive signal output terminal “H”: relay on
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