Sony CMT-C7NT / HCD-C7NT Service Manual ▷ View online
73
HCD-C7NT
IC1007 PCM2702E/2K (MD DIGITAL BOARD)
XTO
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCCP
AGNDP
VCCL
AGNDL
VOUTL
VCC
VCOM
XTI
VDDC
DGNDC
VDD
DGND
D+
D-
VBUS
DGNDU
PLYBCK
SSPND
VOUTR
AGND
AGNDR
VCCR
ZERO
TEST3
TEST2
TEST0
TEST1
USB I/F
8X
OVER-
SAMPLING
DIGITAL
FILTER
MULTI-
LEVEL
DELTA-
SIGMA
MODULATOR
USB
CLOCK
GEN
AUDIO
CLOCK
GEN
OSC
DAC
POWER SUPPLY
LPF
DAC
LPF
SYSTEM CLOCK
74
HCD-C7NT
6-26. IC Pin Function Description
• IC101 CXA2523AR RF Amplifier (BD(MD) Board)
• IC101 CXA2523AR RF Amplifier (BD(MD) Board)
Pin No.
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
Pin Name
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
Description
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2662R
Serial clock input from the CXD2662R
Latch signal input from the CXD2662R “L”: Latch
Stand by signal input “L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2662R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2662R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2662R
FM signal output of ADIP
ADIP signal comparator input ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2662R
I3 signal/temperature signal output to the CXD2662R
(Switching with a serial command)
Focus error signal output to the CXD2662R
Light amount signal output to the CXD2662R
RF/ABCD bottom hold signal output to the CXD2662R
RF/ABCD peak hold signal output to the CXD2662R
RF equalizer output to the CXD2662R
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
75
HCD-C7NT
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD(MD) Board)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
O
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
Pin Name
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
Description
Function FOK signal output to the master controller (monitor output)
“H” is output when focus is on (Not used)
Track jump detection signal output to the master controller (monitor output)
Monitor 2 output to the master controller (monitor output)
Monitor 3 output to the master controller (monitor output) (Not used)
Writing data signal input from the master controller
Serial clock signal input from the master controller
Serial latch signal input from the master controller
Reading data signal output to the master controller
Internal status (SENSE) output to the master controller
Reset signal input from the master controller “L”: Reset
Subcode Q sync (SCOR) output to the master controller
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the master controller
Laser power switching input from the master controller “H”: Recording, “L”: Playback
Interrupt status output to the master controller
Magnetic head ON/OFF control signal output
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input) (Fixed at “L”)
Digital audio output (Optical output) (Open)
Serial data input (Fixed at “L”)
LR clock input “H” : Lch, “L” : R ch (Fixed at “L”)
Serial data clock input (Fixed at “L”)
Data input from the A/D converter
Data output to the D/A converter (Not used)
LR clock output for the A/D and D/A converter (44.1 kHz) (Not used)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
76
HCD-C7NT
Pin No.
48
49
50, 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
I/O
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
Pin Name
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
TEST4
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
Description
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input from the CXA2523AR
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input from the CXA2523AR
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “H”)
ADIP duplex FM signal input from the CXA2523AR (22.05 ± 1 kHz)
Filter f0 control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–) to the BH6519FS
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
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