Sony CMT-BX30R / CMT-BX40R / HCD-BX30R / HCD-BX40R Service Manual ▷ View online
HCD-BX30R/BX40R
37
IC311 BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
IC321, 322 TC74HC4066AFT (EL)
1I/O
VCC
1
14
1C
13
4C
12
4I/O
11
4O/I
10
1O/I 2
2O/I 3
2I/O 4
2C 5
3C 6
GND 7
3O/I
9
3I/O
8
IC323 TC74VHC157FT (EKJ)
SELECT 11
1
1A 2
3
4
5
6
7
INPUT
INPUT
OUTPUT
OUTPUT
1A
1B
1Y
2A
2B
2Y
1B
1Y
2A
2B
2Y
GND 8
V
CC
STROBE
16
4A
15
14
13
11
12
11
10
INPUT
INPUT
OUTPUT
OUTPUT
G
4B
4Y
3A
4A
4B
4Y
3A
3B
9
3B
3Y
3Y
S
– AMP Board –
IC601 STK433-730-E
11
IN/1
10
MONIT
OR
13
ST
-BY
4
CH1+
12
NF/1
8
+PRE
9
GND/SUB
2
-VCC
1
-PRE
3
+VCC
5
CH1-
PRE DRIVE
CH1
FINAL DRIVE
CH1
14
NF/2
6
CH2+
15
IN/2
7
CH2-
PRE DRIVE
CH2
FINAL DRIVE
CH2
STANDBY
CIRCUIT
– PANEL Board –
IC902 PT6302LQ-010
SEGMENT
DRIVER
GRID
DRIVER
CG-RAM
ADDRESS SELECTOR
DC-RAM
CG-ROM
8 BIT
SHIFT
REGISTER
TIMING
GENERATOR 2
TIMING
GENERATOR 1
COMMAND
DECODER
CONTROL
CIRCUIT
PORT
DRIVER
WRITE
ADDRESS
COUNTER
READ
ADDRESS
COUNTER
GR1
32
SG20
16
SG19
15
GR2
33
OSCI 50
VSS 49
VDD 56
RSTB 52
OSCO 51
AD-RAM
DUTY CONTROL
OSCILLATOR
DIGIT CONTROL
CLKB 54
DIN 55
CSB 53
P1 57
P2 58
P2 58
AD
DRIVER
AD2 59
AD1 60
AD1 60
SG4 64
SG3 63
SG2 62
SG1 61
SG35
31
SG34
30
SG33
29
SG32
28
SG31
27
SG30
26
SG29
25
SG28
24
SG27
23
SG26
22
SG25
21
SG24
20
SG23
19
SG22
18
SG21
17
SG18
14
SG17
13
SG16
12
SG15
11
SG14
10
SG13
9
SG12
8
SG1
1
7
SG10
6
SG9
5
SG8
4
SG7
3
SG6
2
SG5
1
GR3
34
GR4
35
GR5
36
GR6
37
GR7
38
GR8
39
GR9
40
GR10
41
GR1
1
42
GR12
43
GR13
44
GR14
45
GR15
46
GR16
47
VEE
48
HCD-BX30R/BX40R
38
• IC Pin Function Description
CD BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR)
CD BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
AVSS3
-
Ground terminal
2
RFZi
I
RF ripple zero crossing signal input terminal
3
RFRP
O
RF ripple signal output terminal
4
SBAD/RFDC
O
Sub beam addition signal or RF peak detection signal output terminal Not used
5
FEi
O
Focus error signal output terminal Not used
6
TEi
O
Tracking error signal output terminal
7
TEZi
I
Tracking error zero crossing signal input terminal
8
AVDD3
-
Power supply terminal (+3.3 V)
9
FOo
O
Focus coil drive signal output terminal
10
TRo
O
Tracking coil drive signal output terminal
11
VREF
I
Reference voltage (+1.65V) input terminal
12
FMO
O
Sled motor drive signal output terminal
13
DMO
O
Spindle motor drive signal output terminal
14
VSSP3
-
Ground terminal
15
VCOi
I
VCO control voltage input terminal
16
VDDP3
-
Power supply terminal (+3.3 V)
17
VDD1
-
Power supply terminal (+1.5 V)
18
VSS1
-
Ground terminal
19
FGiN
I
FG signal input terminal Not used
20
IO0 (/HSO)
I
Disc inner position detection signal input terminal
21
IO1 (/UHSO)
O
Not used
22
XVSS3
-
Ground terminal
23
XI
I
System clock input terminal (16.9344 MHz)
24
XO
O
System clock output terminal (16.9344 MHz)
25
XVDD3
-
Power supply terminal (+3.3 V)
26
DVSS3
-
Ground terminal
27
RO
O
Analog audio (R-ch) signal output terminal
28
DVDD3
-
Power supply terminal (+3.3 V)
29
DVR
O
Reference voltage (+1.65V) output terminal
30
LO
O
Analog audio (L-ch) signal output terminal
31
DVSS3
-
Ground terminal
32
VDDT3
-
Power supply terminal (+3.3 V)
33
VSS1
-
Ground terminal
34
VDD1
-
Power supply terminal (+1.5 V)
35
VDDM1
-
Power supply terminal (+1.5 V)
36
SRAMSTB
I
S-RAM standby mode control signal input terminal Fixed at "L" in this set
37
XRST
I
Reset signal input from the system controller "L": reset
38, 39
BUS0, BUS1
I
Serial data input from the system controller or USB controller
40
BUS2 (SO)
I
Serial data input from the system controller or USB controller
41
BUS3 (SI)
I
Serial data input from the system controller or USB controller
42
BUCK (CLK)
I
Serial data transfer clock signal input from the system controller or USB controller
43
XCCE
I
Chip enable signal input from the system controller or USB controller
44
TEST
I
Setting terminal for test mode Normally fi xed at "L"
45
IRQ
I
Interrupt request signal input terminal
46
AoUT3 (PO4)
O
Not used
47
AoUT2 (PO5)
O
Audio data output to the USB controller
48
PIO0
O
Request signal output to the system controller or USB controller
49
PIO1
O
Request signal output to the USB controller
50
PIO2
O
Not used
51
PIO3
I
Gate signal input from the USB controller
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used
HCD-BX30R/BX40R
39
Pin No.
Pin Name
I/O
Description
56
IPF
O
Not used
57
SFSY/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal Not used
59
GPIN
I
Not used
60
MS
I
Microcomputer interface mode selection signal input terminal Fixed at "H" in this set
61
DOUT (PO6)
O
Digital audio data output terminal Not used
62
AOUT (PO7)
O
Audio data output terminal Not used
63
BCK (PO8)
O
Bit clock signal output to the USB controller
64
LRCK (PO9)
O
L/R sampling clock signal output terminal
65
AIN (PI4)
I
Digital audio data input from USB controller
66
BCKi (PI5)
I
Bit clock signal input from the USB controller
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller
68
VDD1
-
Power supply terminal (+1.5 V)
69
VSS1
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3 V)
72
PDo
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFo
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCo
O
EFM slice level output terminal
81
RFi
I
RF signal input terminal
82
RFRPi
I
RF ripple signal input terminal
83
RFEQo
O
EFM slice level output terminal
84
VRo
O
Reference voltage (+1.65V) output terminal
85
RESiN
O
External resistor connection terminal
86
VMDiR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFo
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3 V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit
"H": laser diode on
"H": laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
96
FPi2 (D)
I
Main beam (D) input from the optical pick-up block
97
FPi1 (B)
I
Main beam (B) input from the optical pick-up block
98
TPi (F)
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
TNi (E)
I
Sub beam (E) input from the optical pick-up block
HCD-BX30R/BX40R
40
USB BOARD IC901 TMP92CD28AFG-7AC9 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
/RESET
I
Reset signal input from the system controller "L": reset
2
DI
I
Ready to send signal input from the system controller
3, 4
NO USE
O
Not used
5
G-3
I
Function selection signal input terminal Fixed at "L" in this set
6
DVCC
-
Power supply terminal (+3.3 V)
7 to 9
NO USE
O
Not used
10
DVSS
-
Ground terminal
11
DVCC
-
Power supply terminal (+3.3 V)
12
RVOUT1
O
Reference voltage (+3.3 V) output terminal
13, 14
RVIN
I
Reference voltage (+3.3 V) input terminal
15
RVOUT2
O
Reference voltage (+3.3 V) output terminal
16
DVCC
-
Power supply terminal (+3.3 V)
17
DVSS
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC
-
Power supply terminal (+3.3 V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC
-
Power supply terminal (+3.3 V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0 to BUS3
O
Serial data output to the CD-MP3 processor
59
/BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
60
/CCE
O
Chip enable signal output to the CD-MP3 processor
61
NO USE
O
Not used
62
DVSS
-
Ground terminal
63
DVCC
-
Power supply terminal (+3.3 V)
64
RD
O
Output enable signal output to the S-RAM
65
WR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
NO USE
O
Not used
69
BOOT
I
Boot mode selection signal input terminal "L": boot mode
70
CS2
O
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input terminal Fixed at "H" in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC
-
Power supply terminal (+3.3 V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB VBUS power on/off control signal output terminal "H": power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal Fixed at "H" in this set
82
NO USE
O
Not used
83
DVSS
-
Ground terminal
84
DO
O
Clear to send signal output to the system controller
85
DATA
I
Audio data input from the CD-MP3 processor
86
CLOCK
I
Audio data transfer clock signal input from CD-MP3 processor
87
TXD1
O
Serial data output to the system controller
88
RXD1
I
Serial data input from the system controller
89
NO USE
O
Not used
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