Sony CFD-S20CP (serv.man4) Service Manual ▷ View online
17
CFD-S20CP
1
LRSY
I
CD L/R clock input
2
ADDATA
O
Audio data output
3
ADBCK
O
Audio bit clock output
4
ADLRCK
O
Audio L/R clock output
5
C2FIN
I
CD C2 error flag input
6
VSS
—
Ground
7
CKIN
I
System clock (16.9344 MHz) input
8
VSS
—
Ground
9
CKOUT
O
Clock (384Fs) output for external DF/DAC.
10
VSS
—
Ground
11
DVDD1
—
Digital power supply pin for I/O.
12
PW
I
CD subcode data serial input
13
SBSY
I
CD subcode block synchronized signal input
14
SFSY
I
CD subcode frame synchronized signal input
15
SBCK
O
Serial clock output for CD subcode transfer. (Not used. (Open))
16
AVDD
—
Analog (PLL) power supply pin
17
VPRFR
—
VCO oscillation range setting pin
18
VCOC
I
VCO control voltage input
19
VPDO
O
VCO charge pump output
20
AVSS
—
Analog ground
21
DVDD2
—
Power supply pin for internal logic.
22
VSS
—
Ground
23 to 30
MDATA0 to 7
I/O
DRAM data bus 0 to 7
31
DVDD3
—
Digital power supply pin for I/O.
32
VSS
—
Ground
33 to 40
MDATA8 to 15
I/O
DRAM data bus 8 to 15
41
RASB
O
Row Address Strobe signal output (L: active)
42
WEB
O
Data Write Enable signal output (L: active)
43
CASLB
O
Column Address Strobe signal output (for lower byte, L: active)
44
CASUB
O
Column Address Strobe signal output (for upper byte, L: active)
45
OEB
O
Output enable signal output (L: active)
46 to 49
MADRS12 to 9
O
DRAM address output 12 to 9 (Not used. (Open))
50
MADRS8
O
DRAM address output 8
51
DVDD4
—
Digital power supply pin for I/O.
52
VSS
—
Ground
53 to 60
MADRS7 to 0
O
DRAM address output 7 to 0
61
DVDD5
—
Power supply pin for internal logic.
62
VSS
—
Ground
63
STREQ
I/O
MP3 data request flag output (H: active)/DRAM data request flag input (H: active)
(Not used. (Open))
64
STCK
I/O
MP3 data transfer clock input/DRAM data transfer clock output (Not used. (Open))
65
STDAT
I/O
MP3 data serial input/DRAM data serial output (Not used. (Open))
66
FSYNC
O
MP3 frame synchronized signal input (H: active) (Not used. (Open))
67
CRCF
O
CDROM-CRC flag output (H: active)/DRAM data output enable signal output
(H: active) (Not used. (Open))
68
DVDD6
—
Power supply pin for internal logic.
69
VSS
—
Ground
70
WOK
I
DRAM write OK input (at CD-DA, H: active)/DRAM data request flag input
(at CD-ROM, H: active)
SECTION 6
DIAGRAMS
6-1. IC PIN DESCRIPTIONS
• IC1001 LC78683E-US-E (MP3 DECODER, CD-ROM DECODER, ANTI-SHOCK CONTROLLER) (CD BOARD)
Pin No.
Pin Name
I/O
Pin Description
18
CFD-S20CP
Pin No.
Pin Name
I/O
Pin Description
71
CNTOK
O
Data connecting point detection completion flag output (at CD-DA, H: active)/DRAM
data serial output (at CD-ROM, H: active) (Not used. (Open))
72
OVF
O
DRAM write discontinue flag output (at CD-DA, H: active)/DRAM data transfer
clock output (at CD-ROM, H: active) (Not used. (Open))
73
CMDOUT
O
Command serial data output (Nch open drain output pin)
74
CMDIN
I
Command serial data input
75
CL
I
Command serial clock input
76
CE
I
Command enable input (H: active)
77
INTB
O
Interrupt signal output (L: active)
78
RESB
I
System reset input (L: active)
79
DATAIN
I
CD serial data input
80
DATACK
I
CD bit clock input
CFD-S20CP
19
19
68
CMDOUT (MP3)
O
Command serial data output
69
CMDIN (MP3)
I
Command serial data input
70
CL (MP3)
O
Command serial clock output
71
N.C
—
Not used. (Open)
72
DRF (CD)
I
CD focus ON/OFF detection signal input
73
DO (CD)
O
CD data output
74
DI (CD)
I
CD data input
75
CL (CD)
O
CD data transfer clock output
76
CE (CD)
O
CD chip enable output
77
FSEQ (CD)
I
CD synchronized signal detection input
78
RES (CD)
O
CD system reset signal output (L: reset)
79
RESB (MP3)
O
MP3 system reset signal output (L: reset)
80
CE (MP3)
O
MP3 chip enable output
81 to 90
N.C
—
Not used. (Open)
91
A-MUTE
O
Audio muting ON/OFF control signal output
92
MEGA BASS
O
MEGA BASS ON/OFF control signal output
93
P-CON
O
System power control output (H: active)
94
V-DATA
O
Volume data output
95
V-CLOCK
O
Volume clock output
96
N.C
—
Not used. (Open)
97
TAPE PLAY
I
Tape playback switch input (L: playback)
98
REC-IN
I
Tape record signal input (H: record)
99
N.C
—
Not used. (Open)
100
VSS
—
Ground
Pin No.
Pin Name
I/O
Pin Description
6-2. CIRCUIT BOARDS LOCATION
• IC801 µPD784216AGF-527-3BA (SYSTEM CONTROLLER) (MAIN BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
TU-CE
O
PLL chip enable output
2
TU-DATA
O
PLL serial data output
3
TU-CLK
O
PLL serial data transfer clock output
4
TU-COUNT
I
PLL serial count data input
5
TU-MUTE
O
Tuner muting ON/OFF control signal output (L: muting ON)
6
DEST1
I
Destination setting input (Fixed at L)
7
DEST2
I
Destination setting input (Fixed at H)
8
TEST-B
O
Fixed at L in this set.
9
VDD
—
Power supply pin (+3.3 V)
10
TEST-A
I
Fixed at L in this set.
11
EEPROM-SCL
O
Serial clock output for EEPROM IC (IC802).
12
EEPROM-SDA
I/O
Serial data bus input from/output for EEPROM IC (IC802).
13 to 16
N.C
—
Not used. (Open)
17, 18
ISS1, 2
O
ISS1, 2 output
19
TU-ON
O
Tuner power ON/OFF control signal output (L: power ON)
20
TAPE-ON
O
Tape power ON/OFF control signal output (L: power ON)
21
CD-ON
O
CD power ON/OFF control signal output (L: power ON)
22
TEST/VPP
I
Fixed at L.
23 to 27
N.C
—
Not used. (Open)
28
MP3-LED
O
MP3 LED drive signal output (L: active)
29
LCD-RST
O
LCD system reset signal output (L: reset)
30
LCD-C/D
O
LCD command data output
31
LCD-CS
O
LCD chip select data output
32
LCD-DATA
O
LCD serial data output
33
LCD-CLK
O
LCD clock output
34
N.C
—
Not used. (Open)
35
FM/AM SHIFT
O
Shift point output for oscillation frequency change.
36
N.C
—
Not used. (Open)
37
VDD
—
Power supply pin (+3.3 V)
38
X2
O
System clock output (5 MHz)
39
X1
I
System clock input (5 MHz)
40
VSS
—
Ground
41
XT2
O
Sub clock output (Not used. (Open))
42
XT1
I
Sub clock input (Not used. (Connect to VSS))
43
RESET
I
System reset signal input (L: reset)
44
AC-CHK
I
AC power supply detection signal input (L: AC in)
45
RMC IN
I
Sircs receiver data input
46
WAKE-UP
I
Wake up signal input
47
N.C
—
Not used. (Open)
48
CD-DOOR
I
CD lid open/close detection switch input (L: close)
49
INTB (MP3)
I
Interrupt request signal input (L: active)
50
WRQ (CD)
I
CD interruption signal input
51
AVDD
—
Power supply pin (+3.3 V)
52
AVREF0
—
Connect to VDD.
53 to 57
KEY1 to 5
I
Key input 1 to 5
58
REG-CHK
I
REG-CHK detection signal input
59
VH
I
High voltage (+9 V) detection signal input for battery check.
60
VM
I
Middle voltage (+4.5 V) detection signal input for battery check.
61
AVSS
—
Analog ground
62, 63
N.C
—
Not used. (Open)
64
AVREF1
—
Connect to VDD.
65 to 67
N.C
—
Not used. (Open)
CONTROL (4) board
TUNER board
TC board
BATTERY (1) board
BATTERY (2) board
MAIN board
CD board
LCD board
HEADPHONE board
POWER board
CONTROL (2) board
CONTROL (3) board
CONTROL (1) board
CFD-S20CP
20
20
A
C
B
F
E
D
A
C
B
D
LD
PD
VR
F
T+
T–
F+
F–
F–
SL+
SL–
SL–
SP+
SP–
E
VREF
LD
PD
LD POWER
CONTROLLER
Q701
APC
FIN2
FIN1
LDD
LDS
TIN2
TIN1
VREF
RF
10
9
11
80
7
79
4
8
20
17
18
TRACKING
COIL
DRIVE
10
7
FOCUS
COIL
DRIVE
TIN
FIN
25
SLIN
SLED
MOTOR
DRIVE
3
SPINDLE
MOTOR
DRIVE
SPIN
VREF
OPIN
MUTE
T+
T–
12
11
F+
F–
26
27
SL+
SL–
2
1
SP+
SP–
TRACKING
COIL
FOCUS
COIL
OPTICAL PICK-UP
BLOCK
(KSS-213R)
M
M
M702
SLED
MOTOR
M701
SPINDLE
MOTOR
SLED/SPINDLE
MOTOR DRIVER,
TRACKING/FOCUS
COIL DRIVER
IC702
S701
(LIMIT)
EFMIN
HFL
AGC
PH(RFENV)
FE
TE
VREF
CONT1
FSEQ
CONT4
DRF
RES
DI
CE
CL
WRQ
DO
XOUT
XIN
LCHO
RCHO
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
CF2
FSX/16MIN
16MOUT
1
3
67
TDD
TD
FD
SP
SL
31
72 25
66
63 61 62
49
48
73
74
75
76
77
78
80
1
2
3
4
5
9
59
58
57
56
55
52
50
65 64
42
45
RF AMP,
SYSTEM SERVO PROCESSOR,
DIGITAL SIGNAL PROCESSOR
IC701
59
48
72 77
74 76 75 50 73
78
X701
16.93MHz
CE(CD)
DI(CD)
CL(CD)
WRQ(CD)
RES(CD)
DRF(CD)
FSEQ(CD)
DO(CD)
79
44
RESB
49
INTB(MP3)
80
CE
70
CL(MP3)
69
CMDIN(MP3)
68
CMDOUT(MP3)
RESB
INTB
CE
CL
CMDIN
CMDOUT
CD DOOR
VH
93
P-CON
58
REG-CHK
SYSTEM CONTROLLER
IC801 (1/2)
CD +3.3V
SWITCH
Q806,808
BATTERY
CHECK
Q804,805
POWER
CONTROLLER
Q807,D802
AUDIO+6V
REG
Q955,D953
POWER
SWITCH
Q952,953
POWER
SWITCH
Q951
D.VDD (3.3V)
COM. 3.3V
CD-CONT
S801
PUSH
OPEN/
CLOSE
VDD (SW)
AUDIO 6V
D901 – 904
RECT
F902
T901
POWER
TRANSFORMER
J901
AC IN
Signal path
: CD
CLV,CAV
CONTROL
PLL
VCEC
SWITCH
ERROR
CORRECTION
AUDIO CD
A/D
CONVERTER,
SERVO
PROCESSOR
FRAME SYNC
DETECT,PROTECT
INSERT
EFM DECODER
INTERPOLATION
MUTE
&
ATTENUATION
DEEMPHASIS
8FS
DIGITAL
FILTER
&
1-bit DAC
SERIAL
OUT
EXTERNAL
AUDIO IN
LPF
SLICE
LEVEL
CONTROL
GENERAL
PURPOSE
PORT
COMMAND
INTERFACE
INTERFACE
CLOCK
GENERATOR
23
15
FD
SL
SP
TD
VREF
VREF
VREF
CD_IN_R
DATACK
LRSY
79
60
DATA IN
ADDATA
ADBCK
ADLRCK
CF2IN
WEB
OEB
CASLB
CASUB
RASB
CKOUT
7
54
41 44 43 45 42
16 30 31 29 15
23-30,33-40
60-53,50
18-21,24-28
2-5,7-10,
35-38,40-43
CKIN
CMDOUT
CMDIN
CL
CE
INTB
INTB
RESB
CMDOUT
CMDIN
CL
CL
CE
INTB
INTB
RESB
CD_IN_ L
DRY BATTERY
SIZE " D "
(IEC DESIGNATION R20)
6PCS,9V
4.5V
4.5V
D/A
CONVERTER
PH/BH
+3.3V
REG
Q957,D957
RADIO 6V
P.VDD (6.2V)
60
VM
20
FDD
SPDO
SLDO
21 22 23
+3.3V
REG
IC803
3.3V
2
3
2
D951
ICP301
Q803
AC-CHK
BATT COM
VDD
AC-HI
U-COM
(VDD)
MDATA0
I
MDATA15
MADRS0
I
MADRS8
WE
OE
LCAS
UCAS
RAS
DQ0-DQ15
A0-A8
MPS DECODER,
CD-ROM DECODER,
ANTI-SHOK
CONTROLLER
IC1001
SDRAM
IC1002
6-3. BLOCK DIAGRAM — CD SECTION —
(Page 21)
(Page 21)
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