Sony CFD-E55L Service Manual ▷ View online
– 43 –
– 44 –
•
LCD BOARD IC501 CXP83620-011Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
C-SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2589Q (IC703)
2
RMC
I
Sircs remote control signal input terminal Not used (fixed at “L”)
3
BUZZER
O
Buzzer sound signal output terminal
4
LED
O
LED drive signal output of the ALARM indicator (D602) “L”: LED on
5
C-SENS
I
Internal status signal (sense signal) input from the CXD2589Q (IC703)
6
C-SENS2
I
Internal status signal (sense signal) input from the CXA1992BR (IC701)
7
C-SQCK
O
Subcode Q data reading clock signal output to the CXD2589Q (IC703)
8
C-SQSO
I
Subcode Q data input from the CXD2589Q (IC703)
9
C-RST
O
System reset signal output to the CXA1992BR (IC701) and CXD2589Q (IC703) “L”: reset
10
C-CLOCK
O
Serial data transfer clock signal output to the CXD2589Q (IC703)
11
C-LATCH
O
Serial data latch pulse signal output to the CXD2589Q (IC703)
12
C-DATA
O
Serial data output to the CXD2589Q (IC703)
13
REC
I
Record/playback detection signal input terminal “L”: recording mode, “H”: playback mode
14
R-COUNT
I
PLL serial data input from the FM/AM PLL (IC2)
15
R-DATA
O
PLL serial data output to the FM/AM PLL (IC2)
16
R-CLOCK
O
PLL serial data transfer clock signal output to the FM/AM PLL (IC2)
17
R-LATCH
O
PLL serial data latch pulse signal output to the FM/AM PLL (IC2)
18
V-LATCH
O
Serial data latch pulse signal output to the electrical volume (IC302)
19
V-DATA
O
Serial data output to the electrical volume (IC302)
20
V-CLOCK
O
Serial data transfer clock signal output to the electrical volume (IC302)
21
P-CON
O
Power on/off control signal output to the power supply circuit, and power amplifier (IC303)
“L”: standby mode, “H”: power on
“L”: standby mode, “H”: power on
22
DC1
I
DC level check input of the dry battery and AC input (+9V check) (A/D input)
23
DC2
I
DC level check input of the dry battery (+6V check) (A/D input)
24
DC3
I
DC level check input of the dry battery (+3V check) (A/D input)
25
KEY1
I
Key input terminal (A/D input) S601 to S606 (ALARM, TIMER, SLEEP, DSPL ENT MEM,
PLAY MODE MONO/ST ISS, SOUND keys input)
PLAY MODE MONO/ST ISS, SOUND keys input)
26
KEY2
I
Key input terminal (A/D input) S609 to S615 (x, u, CLOCK, MEGA BASS, START/
STOP, . # TUNE TIME SET, > 3 TUNE TIME SET keys input)
STOP, . # TUNE TIME SET, > 3 TUNE TIME SET keys input)
27
KEY3
I
Key input terminal (A/D input) S617, S619 to S624 (OPERATE, RADIO BAND, VOL +, VOL
–, PRESET –, PRESET +, AUTO PRESET keys input)
–, PRESET –, PRESET +, AUTO PRESET keys input)
28
MODE CHECK
I
Destination setting terminal
29
SHIFT CLOCK
O
Shift clock output of the main system clock (4.19 MHz) “H”: active
Initial setting signal output terminal
Initial setting signal output terminal
30
RST
I
System reset signal input from the reset signal generator (IC503) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (4.19 MHz)
32
XTAL
O
Main system clock output terminal (4.19 MHz)
33
VSS
—
Ground terminal
34
VL
O
Liquid crystal display drive bias control signal output terminal
35 to 37
VLC3 to VLC1
—
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
38 to 41
COM0 to COM3
O
Common drive signal output to the liquid crystal display (LCD501)
42 to 64
SEG0 to SEG22
O
Segment drive signal output to the liquid crystal display (LCD501)
65
MOTOR ON
O
Capstan/reel motor (M301) on/off control signal output terminal
66
A-MUTE
O
Audio muting on/off control signal output to the electrical volume (IC302) “H”: muting on
Pin No.
Pin Name
I/O
Description
67
B-MUTE
O
Tuner muting on/off control signal output terminal “H”: muting on
68
C-MUTE
O
Digital muting on/off control signal output to the CXD2589Q (IC703) “H”: muting on
69
TAPE
O
Tape function control signal output to the TA2068N (IC301)
“L”: radio or CD on, “H”: tape on
“L”: radio or CD on, “H”: tape on
70
RADIO
O
Power on/off control signal output for the radio +6V power supply “H”: radio power on
71
CD
O
Power on/off control signal output for the CD +5V power supply, and CD function control signal
output to the TA2068N (IC301) “L”: CD power on (CD on)
output to the TA2068N (IC301) “L”: CD power on (CD on)
72
VDD
—
Power supply terminal (+5V)
73
TX
O
Sub system clock output terminal (32.768 kHz)
74
TEX
I
Sub system clock input terminal (32.768 kHz)
75
NC
O
Not used (open)
76
ISS1
O
ISS 1 on/off control signal output terminal “H”: ISS 1 on
77
ISS2
O
ISS 2 on/off control signal output terminal “H”: ISS 2 on
78
C-DOOR
I
CD lid open/close detection switch (S701) input terminal “L”: CD lid is closed
79
TC-PLAY
I
Tape play detection switch (S304) input terminal “L”: tape play mode
80
REG CHK
I
Regulator check signal input of the AC input or battery input “H”: active
6-10.
IC PIN FUNCTION DESCRIPTION
CFD-E55L
– 45 –
– 46 –
6-11.
PRINTED WIRING BOARDS – DISPLAY Section –
•
See page 26 for Circuit Boards Location.
Note on Printed Wiring Boards:
•
•
X
: parts extracted from the component side.
•
Y
: parts extracted from the conductor side.
•
b
: Pattern from the side which enables seeing.
Ref. No.
Location
Ref. No.
Location
• Semiconductor Location
D601
A-8
D602
A-8
IC501
C-5
IC502
B-6
IC503
C-3
Q501
B-6
Q502
B-6
Q503
D-4
Q504
C-4
Q505
C-4
2
1
1
2
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
05
(Page 32)
(Page 32)
(Page 27)
(Page 33)
CFD-E55L
– 47 –
– 48 –
– 49 –
6-12.
SCHEMATIC DIAGRAM – DISPLAY Section –
•
See page 38 for Waveforms.
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
C
: panel designation.
•
U
: B+ Line.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : TUNER
(
no mark : TUNER
(
) : CD
〈〈
〉〉
: TAPE
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Circled numbers refer to waveforms.
(Page 40)
(Page 40)
(Page 31)
(Page 36)
– 50 –
– 51 –
– 52 –
• IC Block Diagrams
– CD Board –
– CD Board –
IC701
CXA1992BR
IC702
BA6898FP
IC703
CXD2589Q
– MAIN Board –
IC1
TA2104BN
IC2
LC72137-D
FZC
VC
TDFCT
TZC
ATSC
TEI
LPFI
TEO
VEE
EI
E
F
FE
BIAS
SL P
SL M
SL O
ISET
VCC
XRST
DATA
DATA
XLT
CLK
CLK
LOCK
SENS2
SENS1
C. OUT
VCC
DFCTO
IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4
FS1 – FS4
TG1 – TG2
TM1 – TM7
PS1 – PS4
TGH
TGL
BALH
BALL
ATSC
DFCT
TM1
TG1
FS2
IFB1 – IFB6
VCC
VEE
VCC
VEE
VEE
PD 2
I-V AMP
FOK
CC2
CC1
CB
CP
RF O
RF I
RFTC
PD2
PD1
PD
LD
RF M
TA
O
TA
M
FSET
TG2
TGU
SRCH
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
TZC
FZC
FOL
FOH
MIRR
LDON
LPCL
LPC
TGFL
DFCT1
CC1
1
2
3
4
5
6
7
8
9
10
26
25
24
23
22
21
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
39
PD 1
I-V AMP
38
PD
AMP
37
LD
AMP
LASER
POWER
CONTROL
FOCUS BIAS
WINDOW
COMPARATOR
FOCUS ERROR
AMP
F I-V
AMP
AMP
E I-V
AMP
AMP
TGFL
TRACKING GAIN
WINDOW
COMPARATOR
E-F BALANCE
WINDOW
COMPARATOR
ATSC
WINDOW
COMPARATOR
TZC
COMPARATOR
TRACKING PHASE
COMPENSATION
CENTER
VOLTAGE
GENERATOR
FZC
COMPARATOR
FOCUS PHASE
COMPENSATION
CHARGE UP
FSET
ISET
IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
OUTPUT DECODER
TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
RF SUMMING
AMP
FOCUS OK
COMPARATOR
PEAK/BOTTOM
HOLD
PEAK/BOTTOM
HOLD
DEFECT
AMP
MIRR
COMPARATOR
36
34
31 30
29
28
27
35
33 32
BAL1 – BAL4
TM6
TM2
VCC
VEE
TM5
11
12
13
TG2
TM4
VCC
VEE
TM3
FS1
VCC
VEE
TOG1 – TOG4
TM7
FS4
DFCT
+
–
+
–
+
–
LEVEL SHIFT
28
27
26
25
24
22
21
20
19
18
17
16
+
–
LEVEL SHIFT
+
–
VCC
VCC
+
–
–
LEVEL SHIFT
+
–
–
LEVEL SHIFT
1
2
3 4 5 6
7 8
9 10
11
12 13
14
REGULATOR
BIAS, T. S. D
BIAS, T. S. D
MONITOR
+
–
DRIVER
MUTE
+
–
15
23
NC
GND
OUT4-B
OUT4-A
IN4
IN4
,
VREF IN
VCC
VCC
IN3
,
IN3
OUT3-A
OUT3-B
NC
OPIN-B
OPOUT
GND
OUT2-B
OUT2-A
IN2
IN2
,
GND
MUTE
REGOUT
REG-B
RESET
IN1
OUT1-B
OUT1-A
PWM
PWM
1
2 3
4 5 6
12
13
14
15 16 17
19 20
34
27
24
23
25
21
61
63
64
66
67
68
69
70
71
72
73
74
75
77
78
79
80
OSC
62
65
76
7 8 9
10
11
18
22
28
26
33
32
31
30
29
36
35
40
39
38
37
45
44
43
42
41
50
49
48
47
46
55
54 53 52 51
59 58 57
56
60
EFM
DEMODULATOR
ERROR
CORRECTOR
16k
RAM
D/A
INTERFACE
CLOCK
GENERATOR
SERVO
AUTO
SEQUENCER
CPU
INTERFACE
DIGITAL
OUT
SUB CODE
PROCESSOR
3rd-ORDER
NOISE SHAPER
OVER SAMPLING
DIGITAL FILTER
SERIAL-IN
INTERFACE
DIGITAL
CLV
OSC
DIGITAL
PLL
ASYMMETRY
CORRECTOR
LRCKI
LRCK
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
V16M
VCTL
VCTL
VCKI
VPCO1
TES1
TES0
PWMI
MDP
VDD
SYSM
AVSS
AVDD
XTAI
XVDD
AVSS
LOUT1
AIN1
AOUT1
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
XRST
XRST
VDD
VSS
EXCK
SBSO
SCOR
WFCK
ENPHI
EMPH
DOUT
C4M
XTSL
C2PO
GFS
XPCK
XUGF
VDD
VSS
BCKI
BCK
PCMDI
PCMD
VSS
LMUTE
RMUTE
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
XLON
FOK
VDD
VSS
GND1
3
2
1
IF REQ
AM
MIX
FM RF IN
AM LOW OUT
5
4
MIX OUT
VCC2
AM IF IN
8
7
6
FM IF IN
GND2
10
9
AGC
QUAD
12
11
R OUT
L OUT
FM RF OUT
22
23
24
20
21
17
18
19
15
16
13
14
AM RF IN
VCC1
FM OSC
ST IND
OSC OUT
AM OSC
IF OUT
LPF2/MO-ST
MPX IN
DET OUT
LPF1/BAND
FM
MIX
FM
OSC
LEVEL
DET
AM
DET
MUTE
FM
DET
ST/MO
FM/AM
AM
OSC
AGC
SW
ST
1/8
BUFF
BUFF
DIVIDE
DECODE
VCO
IF BUFF
AF BUFF
AF
FM RF
AM IF
FM IF
12
11
10
9
8
7
6
5
4
3
2
1
13
14
15
16
17
20
21
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
NC
CE
DI
CL
DO
XOUT
22 NC
AOUT
XIN
AIN
PD
VSS
VDD
B04
FMIN
AMIN
B01
B02
B03
I01
I02
IFIN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
18
19
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