Sony CDP-XE510 Service Manual ▷ View online
— 9 —
6. Check the level B of the oscilliscope's waveform and the A (DC
voltage) of the center of the Traverse waveform.
Confirm the following :
A/B x 100 = less than ± 22%
Confirm the following :
A/B x 100 = less than ± 22%
Traverse waveform
Center of the waveform
B
level : 1.3 ± 0.6 Vp-p
0V
A (DC voltage)
7. Press the “8” button. (The tracking servo and sledding servo are
turned ON.) Confirm the C (DC voltage) is almost equal to the
A (DC voltage) is step 6.
A (DC voltage) is step 6.
Traverse waveform
0V
Tracking servo
Sledding servo
OFF
Tracking servo
Sledding servo
ON
C (DC
voltage)
voltage)
8. Disconnect the lead wire of TP1 (ADJ) connected in step 1.
RF PLL Free-run Frequency Check
Procedure :
1. Connect frequency counter to test point (PLCK) with lead wire.
1. Connect frequency counter to test point (PLCK) with lead wire.
2. Turn Power switch on.
3. Put the disc (YEDS-18) in to play the number five track.
3. Put the disc (YEDS-18) in to play the number five track.
Confirm that reading on frequency counter is 4.3218MHz.
Adjustment Location :
[ BD BOARD ] — Side A —
[ MAIN BOARD ] — Component Side —
frequency counter
BD board
TP (PLCK)
(PLCK)
IC101
10
1
IC103
20
(RF)
(VC)
11
(TE)
(FEI)
(FE)
TP1 (ADJ)
TP2 (AFADJ)
R622
J681
IC651
CN621
IC631
R621
IC621
J621
— 10 —
SECTION 6
DIAGRAMS
6-1. IC BLOCK DIAGRAMS
IC101 CXD2545Q
68
67 62 63 64
20 19
C4M
FSTO
XTAI
XTAO
XTSL
VCKI
VPCO
69
C16M
43 PSSL
18
PDO
13
VCO1
12
VCO0
33
PCO
32
FILI
31
FILO
34
CLTV
36
RFAC
38
ASYI
39
ASYO
42
ASYE
73
WFCK
74
SCOR
76
EXCK
75
SBSO
72
EMPH
78
SQCK
77
SQSO
95
MON
94
FSW
96
MDP
97
MDS
26
RFDC
27
TE
28
SE
29
FE
30
25
VC
RFC
CLOCK
GENERATOR
ASYMMETRY
CORRECTION
CORRECTION
DIGITAL
PLL
VARI-PITCH
(
DOUBLE SPEED
)
EFM
DEMODULATOR
TIMING
GENERATOR 1
TIMING
GENERATOR 2
CLV
PROCESSOR
FOCUS SERVO
MIRR
DFCT
FOK DETECTOR
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
SERVO
MICRO PROGRAM
INTERFACE
SERVO
AUTO
SEQUENCER
SERIAL
PARALLEL
PROCESSOR
18-TIMES
OVERSAMPLING
FILTER
SWITCH
&
BUFFER
A/D
CONVERTER
SYNC
PROTECTOR
D/A
DATA PROCESSOR
ADDRESS
GENERATOR
PRIORITY
ENCODER
ENCODER
NOISE
SHAPER
MUX
CPU INTERFACE
32K RAM
RESISTER
ERROR CORRECTOR
PEAK DETECTOR
DIGITAL OUT
24
ADIO
21
AVDD
40
AVDD
23
AVSS
35
AVSS
41
ADD
90
ADD
15
DVSS
65
DVSS
81
XRST
22
IGEN
37
BIAS
44
WDCK
45
LRCK
66
FSTI
82
DIRC
83
SCLK
84
DFSW
85
ATSK
98
LOCK
99
SRON, SRDR
1, 2
SFON, SFDR
3, 100
DA01-16
61-46
TFDR, TFON
4, 7
TRON, TRDR
5, 6
FFDR, FFON
8, 11
FRON, FRDR
9, 10
SSTP
16
TES2
14
TEST
17
TES3
TRACKING
SERVO
SLED PWM
GENERATOR
2
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
SLED SERVO
SERVO DSP
PWM GENERATOR
2
2
2
2
2
93 FOK
92 DFCT
91 MIRR
80 SENS
89 COUT
88 CLOK
86 DATA
71 D OUT
79 MUTE
70 MD2
87 XLAT
16
IC102 BA6392FP-T1
BUFF
BUFF
BUFF
BUFF
R
R
F
F
1
CH1 OUT F
2
CH1 OUT R
3
CAPA IN 1
4
CH1 R IN
5
CH1 F IN
6
VREF IN
7
VREF OUT
8
GND
9
CH2 F IN
10
CH2 R IN
11
CAPA IN 2
12
CH2 OUT R
13
CH2 OUT F
14
GND
28 GND
27 CH4 OUT F
26 CH4 OUT R
25 VB IN
24 VS IN
23 VB IN
22 VCC
21 VCC
20 CH3 F IN
19 CH3 R IN
18 CAPA IN 3
17 CH3 OUT R
16 CH3 OUT F
15 MUTE
LEVEL
SHIFT
INTERFACE
BUFF
BUFF
BUFF
BUFF
R
F
R
F
BUFF
INTERFACE
INTERFACE
F
F
R
R
MUTE
— 11 —
IC103 CXA1821M-T6
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VDD
DQSY
SRDT
SCLK
SW2
SW1
TEST
EXCK
SBSO
SCOR
WFCK
MCK
XMODE
GND
32 WORD X 8 BIT
DUAL PORT RAM
DUAL PORT RAM
TIMING
&
SYNCHRONIZATION
SIGNAL
PROTECTION
CRC
CHECKER
CPU INTERFACE
VDD
3
6
7
2
5
1
4
9
8
10
ON/OFF
AMP
V REF
AMP
RESET
VOMUTE
CD
VIN
VO
RES
CN
GND
EN
VID
VOD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LD
VCC
VCC
PD
LD ON
A
LC/PD
B
RFE
C
RFO
D
FE
VEE
FE BIAS
F
TE
E
VC
VC
VC BUFFER
TRACKING ERROR AMP
FOCUS ERROR AMP
RF EQ AMP
APC LD AMP
RF SUMMING AMP
EI
EO
VEE
VCC
VCC
VC
VC
VC
VC
VC
VC
VC
VEE
VEE
VEE
VREF
IC611 LA5601
IC104 LC89170M-TLM
— 12 —
IC631 LB1641
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
1
INIT
2
3
4
5
6
7
8
9
10
11
12
13
14
D Vdd 2
SYSM
L1 (+)
ATT
A Vdd L
SHIFT
L2 (+)
LATCH
A Vss L
256FSO
X Vss
TEST1
512IN
D Vss
X OUT
MCKSEL
X Vdd
XBCK
A Vss R
DATA
R2 (+)
LRCK
A Vdd R
MUTE L
R1 (+)
MUTE R
D Vdd 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MODE
S/P
ATT
IIR
FIR3
FIR2
FIR1
PLM
PLM
MUTE
CIRCUIT
CLOCK
GENERATOR
AC
DITHER
DC
DITHER
3RD ORDER
NOISE SHAPER
SAMPLE
HOLD (X1)
TIMING CIRCUIT
IC661 CXD8567AM
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