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Model
CDP-XA50ES
Pages
54
Size
4.95 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
cdp-xa50es.pdf
Date
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– 51 –
– 52 –
– AUDIO Section –
1
2
3
4
5
6
7
8
9
NC
OUTPUT 2
Vcc
GND
NC
INPUT 2
INPUT 1
NC
MOTOR
DRIVE
MOTOR
DRIVE
REG
SWITCH
SWITCH
OUTPUT1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
56
55
54
53
52
51 50 49 48 47
57
58
59
60
61
62
63
64
S/P
TIMING CIRCUIT
INTERPOLATER
INTERPOLATER
THIRD ORDER
NOISE SHAPER
THIRD ORDER
NOISE SHAPER
PLM
PLM
CLOCK
GENERATOR
SYNC
COEF
SPLM
18/20
DVDDR
VSUB (D) R
VSUB (CHIP) R
VDD2
VDD
R1 (–)
VSS
R1 (+)
VSS2
VSS2
L1 (+)
VSS
L1 (–)
VDD
VDD2
VSUB (CHIP) L
VSUB (D) L
DVDDL
TEST3
TEST2
TEST1
DATAOUT
 ON/OFF
VSS2
L2 (+)
VSS
L2 (–)
VDD
VDD2
VSUB (A) L
XVDD
XOUT
XIN
XVSS
XVSS
VSUB (A) R
VDD2
VDD
R2 (–)
VSS
R2 (+)
VSS2
DRI
LRCKI
MUTEL
MUTER
INIT
DVSSL
DVSSR
512FSO
BCKI
DLI
DRO
LRCKO
INAF
DINIT
128FS
DPO/BCKO
DM2/SDRO
DM1/SDLO
DLO
6
CLR
7
PR
8
VCC
5
Q
R
S
Q
3
Q
2
D
4
GND
1
CK
Q
D
C
3rd order
NOISE
SHAPER
S / P
TIMING
CIRCUIT
CLOCK
GENERATOR
DATA SELECT  
DATA SELECT  
P/S CONVERT
&
D/F-CLK GEN.
4BIT DATA
BITSTREAM
"0" DETECT
MUTE
CIRCUIT
OR
3rd order
NOISE
SHAPER
L . I . P.
ATT
x 0.75
L . I . P.
ATT
x 0.75
DITHER
OVERFLOW DETECTOR
FIR 4
MODE
INAF
OVFLAG
MUTER
MUTEL
MTPOL
DRPOL
MODE
NC
DFDTOR
DFLRCKO
TEST4
TEST3
VSS
IF SELD
IF SELC
NC
SBCKI
SDATAR
SDATAL
NC
DFDTOL
DFBCKO
DFDTEN
TEST1
TEST2
VSS
PLMG2
VDD
NSDOL4
NSDOL3
NSDOL2
NSDOL1
NC
NC
VDD
VDD
NC
64FSI
NSDOR1
NSDOR2
NSDOR3
NSDOR4
MCKIN
VDD
PLMG1
NRGCLR
SYSM
LATCH
SHIFT
ATT
INIT
LRCKI
DATAI
BCKI
VSS
VSS
NC
INVO2
INVO1
INVI
NC
128FSO
CKVDD
DINIT
52
53
54
55
56
57
58
59
60
61
62
63
64
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
32
31
30
29
28
27
26
25
24
23
22
21
20
FIR 2
FIR 1
FIR 3
ATT
IIR
OVERFLOW DETECTOR
FIR 4
FIR 2
FIR 1
FIR 3
ATT
IIR
POLALITY
2
IC350
BA6208
IC603
CXD2562Q-CS
IC601
CXD8679Q
IC610
TC7W74F
– PANEL Section –
IC801-803
LC7570E
SHIFT REGISTER
A/D CONVERTER
LATCH, FL DRIVER
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S26
S27
S28
S29
S30
S31
S32
S33
SIN
VSS
BLK
NC
NC
S25
S24
S22
S21
NC
S20
S19
S18
S17
NC
S23
NC
VDA
DAT
A
CL
WR
VFL
S0
S1
S2
S3
NC
S4
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
46
47
48
45 44 43 42 41 40 39 38 37
IC404, 504
CXA8042AS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SWITCHING
CIRCUIT
CONSTANT
CURRENT
CIRCUIT
REFERENCE
VOLTAGE
CIRCUIT
CONTROL
CIRCUIT
I01+
IN2–
IN2+
NC
IN1+
IN1–
NC
C4
C3
GND2
VEE2
VEE1
C6
C5
CIREF
I02–
NC
I01–
I02+
NC
VCC2
C2
C1
VCC1
VREF
VCNT
GND1
RIREF
• Waveforms
– SERVO Section –
5.2 Vp-p
474 ns
2
IC101 
@¶
 (TE)  200 mV/DIV, 100 µs/DIV
5.2 Vp-p
16.9344 MHz
3
IC101 
@ª
 (FE)  200 mV/DIV, 50 ns/DIV
4
IC101 
#§
 (RFAC)  200 mV/DIV, 500 ns/DIV
5
IC101
$∞
 (LRCK)
5.2 Vp-p
22.7 
µ
s
4.8 Vp-p
4 MHz
1
IC101 
@§
 (RFDC)  200 mV/DIV, 500 ns/DIV
6
IC101 
$¶
 (BLCK)
7
IC101 
^™
 (XTAI)
8
IC101 
(§
 (MDP)
9
IC201 
#¡
 (XTALI)
– 53 –
– 54 –
840 mVp-p
45.159 MHz
1.8 Vp-p
16.9344 MHz
4 Vp-p
44 ns
1
IC602 
1
– AUDIO Section –
2
IC602 
6
3
IC603 
0
 (XIN)
4
IC604 
3
5
IC610 
1
 (CK)
1.2       Vp-p
+0.25
–0.20
Approx. 400 mVp-p
Approx. 200 mVp-p
1.2       Vp-p
+0.25
–0.20
2.8 Vp-p
8 ns
4.8 Vp-p
180 ns
6-9.
IC  PIN  FUNCTION  DESCRIPTION
   
Pin No. Pin Name
I / O
Function
1
SRON
O
Sled servo drive PWM signal output terminal    Not used (open)
2
SRDR
O
Sled servo drive PWM signal (–) output to the BA6297AFP (IC102)
3
SFON
O
Sled servo drive PWM signal output terminal    Not used (open)
4
TFDR
O
Tracking servo drive PWM signal (–) output to the BA6297AFP (IC102)
5
TRON
O
Tracking servo drive PWM signal output terminal    Not used (open)
6
TRDR
O
Tracking servo drive PWM signal (+) output to the BA6297AFP (IC102)
7
TFON
O
Tracking servo drive PWM signal output terminal    Not used (open)
8
FFDR
O
Focus servo drive PWM signal (+) output to the BA6297AFP (IC102)
9
FRON
O
Focus servo drive PWM signal output terminal    Not used (open)
10
FRDR
O
Focus servo drive PWM signal (–) output to the BA6297AFP (IC102)
11
FFON
O
Focus servo drive PWM signal output terminal    Not used (open)
12
VCOO
O
Oscillator circuit output terminal for analog PLL of the playback EFM    Not used (open)
13
VCOI
I
Oscillator circuit input terminal for analog PLL of the playback EFM    Not used (fixed at “L”)
14
TEST
I
Input terminal for the test (fixed at “L”)
15
DVSS
—
Ground terminal (digital system)
16
TES2
I
Input terminal for the test (fixed at “L”)
17
TES3
I
Input terminal for the test (fixed at “L”)
18
PDO
O
Charge-pump output terminal for analog PLL of the playback EFM    Not used (open)
19
VPCO
O
PLL charge-pump output terminal for the variable pitch    Not used (open)
20
VCKI
I
Clock signal input from external VCO for the variable pitch    Not used (fixed at “L”)
21
AVD2
—
Power supply terminal (+5V) (analog system)
22
IGEN
I
Power supply terminal (+5V) (for operational amplifier)
23
AVS2
—
Ground terminal (analog system)
24
ADII
I
Input terminal for the A/D converter    Not used (open)
25
ADIO
O
Output terminal of the operational amplifier    Not used (open)
26
RFDC
I
RF signal (DC level) input terminal for the digital servo process
27
TE
I
Tracking error signal input from the RF amplifier in optical pick-up
28
SE
I
Sled error signal input from the RF amplifier in optical pick-up
29
FE
I
Focus error signal input from the RF amplifier in optical pick-up
30
VC
I
Middle point voltage (+2.5V) input from the RF amplifier in optical pick-up
31
FILO
O
Filter output terminal for master clock of the playback master PLL
32
FILI
I
Filter input terminal for master clock of the playback master PLL
33
PCO
O
Phase comparison output terminal for master clock of the playback EFM master PLL
34
CLTV
I
Internal VCO control voltage input of the playback master PLL
35
AVS1
—
Ground terminal (analog system)
36
RFAC
I
RF signal (AC level) input terminal for the EFM demodulator
37
BIAS
I
Constant current input terminal of the playback EFM asymmetry circuit
38
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
39
ASYO
O
Playback EFM full-swing output terminal
40
AVD1
—
Power supply terminal (+5V) (analog system)
41
DVDD
—
Power supply terminal (+5V) (digital system)
42
ASYE
I
Playback EFM asymmetry circuit on/off selection input terminal (fixed at “H”)
43
PSSL
I
Audio data output mode selection input terminal (fixed at “L”)
SERVO BOARD   IC101   CXD2545Q
(DIGITAL SIGNAL PROCESSOR,  FOCUS/TRACKING/SLED SERVO, EFM COMPARATOR)
4.8 Vp-p
22 ns
– 55 –
Pin No. Pin Name
I / O
Function
44
WDCK
O
Word clock signal (88.2 kHz) output terminal    Not used (open)
45
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD8679Q (IC601)
46
DATA
O
DA16 output when PSSL=“H”, 48-bit slot serial data output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)    Serial data output to the CXD8679Q (IC601)
47
BCLK
O
DA15 output when PSSL=“H”, 48-bit slot bit clock signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)    Bit clock signal (2.8224 MHz) output to the CXD8679Q (IC601)
48
64 DATA
O
DA14 output when PSSL=“H”, 64-bit slot serial data output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
49
64 BCLK
O
DA13 output when PSSL=“H”, 64-bit slot bit clock signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
50
64 LRCK
O
DA12 output when PSSL=“H”, 64-bit slot L/R sampling clock signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
51
GTOP
O
DA11 output when PSSL=“H”, GTOP signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
52
XUGF
O
DA10 output when PSSL=“H”, XUGF signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
53
XPLCK
O
DA09 output when PSSL=“H”, XPLCK signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
54
GFS
O
DA08 output when PSSL=“H”, GFS (guard frame sync) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
55
RFCK
O
DA07 output when PSSL=“H”, RFCK (read frame clock) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
56
C2PO
O
DA06 output when PSSL=“H”, C2PO signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
57
XRAOF
O
DA05 output when PSSL=“H”, XRAOF (RAM over flow) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
58
MNT3
O
DA04 output when PSSL=“H”, MNT3 (monitor 3) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
59
MNT2
O
DA03 output when PSSL=“H”, MNT2 (monitor 2) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
60
MNT1
O
DA02 output when PSSL=“H”, MNT1 (monitor 1) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
61
MNT0
O
DA01 output when PSSL=“H”, MNT0 (monitor 0) signal output when PSSL=“L”
(PSSL (pin $£)=fixed at “L”)      Not used (open)
62
XTAI
I
System clock input terminal (16 MHz)
63
XTAO
O
System clock output terminal (16 MHz)    Not used (open)
64
XTSL
I
System clock selection input terminal (fixed at “L”)
65
DVSS
—
Ground terminal (digital system)
66
FSTI
I
2/3 divider input terminal of pins ^™ (XATI) and ^£ (XTAO)
67
FSTO
O
2/3 divider output terminal of pins ^™ (XATI) and ^£ (XTAO)
68
C4M
O
4.2336 MHz clock signal output terminal   Not used (open)
69
C16M
O
16.9344 MHz clock signal output terminal   Not used (open)
70
MD2
I
Digital out on/off control signal input from the system controller (IC201)
71
DOUT
O
Digital signal (for coaxial out and optical out) output terminal
72
EMPH
O
Emphasis control signal output terminal    Not used (open)
73
WFCK
O
Write frame clock signal output terminal    Not used (open)
74
SCOR
O
Sub-code sync (S0+S1) detection signal output to the system controller (IC201)
– 56 –
Pin No. Pin Name
I / O
Function
75
SBSO
O
Sub-code P-W serial data output terminal    Not used (open)
76
EXCK
I
Sub-code P-W serial data reading clock signal input terminal    Not used (fixed at “L”)
77
SUBQ
O
Sub-code Q data signal output to the system controller (IC201)
78
SQCK
I
Sub-code Q data reading clock signal input from the system controller (IC201)
79
MUTE
I
Mute signal input from the system controller (IC201)
80
SENS
O
Internal status (SENSE) signal output to the system controller (IC201)
81
XRST
I
System reset signal input from the reset signal generator (IC91)    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
82
DIRC
I
1-track jump mode input terminal    Not used (fixed at “H”)
83
SCLK
I
Sense serial data reading clock signal input from the system controller (IC201)
84
DFSW
I
Defect on/off select signal input terminal    Not used (fixed at “L”)
85
ATSK
I
Input terminal for the anti-shock    Not used (fixed at “L”)
86
DATA
I
Serial data input from the system controller (IC201)
87
XLAT
I
Serial data latch pulse signal input from the system controller (IC201)
88
CLOK
I
Serial data transfer clock signal input from the system controller (IC201)
89
COUT
O
Track number count signal output terminal    Not used (open)
90
DVDD
—
Power supply terminal (+5V) (digital system)
91
MIRR
O
Mirror detection signal output terminal    Not used (open)
92
DFCT
O
Defect signal output terminal    Not used (open)
93
FOK
O
Focus OK signal output terminal    Not used (open)
94
FSW
O
Selection signal output terminal of the output filter for spindle motor    Not used (open)
95
MON
O
Spindle motor on/off control signal output terminal    Not used (open)
96
MDP
O
Spindle servo control signal output terminal
97
MDS
O
Spindle servo control signal output terminal    Not used (open)
98
LOCK
O
GFS is sampled by 460 Hz    “H” output when GFS is “H”    Not used (open)
99
SSTP
I
Detection input from the sled limit-in detect switch (S22)
The optical pick-up is inner position when “H”
100
SFDR
O
Sled servo drive PWM signal (+) output to the BA6297AFP (IC102)
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