Sony CDP-M205 / CDP-M305 Service Manual ▷ View online
– 9 –
Pin No.
Pin name
I/O
Description.
37
VCTL
I
VCO2 control voltage input
38
PCO
O
Charge-pump output to master PLL
39
FILO
O
Filter output to master PLL
40
FILI
I
Filter input for master PLL
41
AVSS
–
Analog ground
42
CLTV
I
Control voltage input for VCO
43
AVDD
–
Analog power supply
44
RF
I
EFM signal input
45
BIAS
I
Asymmetry circuit constant current input
46
ASYI
I
Asymmetry comparate voltage input
47
ASYO
O
EFM full swing output (“L” =VSS, “H” =VDD)
48
ASYE
I
Asymmetry circuit ON/OFF (“L”=OFF, “H”=ON)
49
WDCK
O
D/A interface Word clock f=2fs (Not used)
50
LRCK
O
D/A interface LR clock output f=Fs
51
LRCKI
I
D/A interface LR clock input f=Fs
52
PCMD
O
D/A interface Serial data output
53
PCMDI
I
D/A interface Serial data input
54
BCK
O
D/A interface Bit clock output
55
BCKI
I
D/A interface Bit clock input
56
VSS
–
Ground
57
VDD
–
+5V power supply
58
GTOP
–
Not used
59
XUGF
–
Not used
60
XPLCK
O
EFM decoder PLL clock output
61
GFS
O
“H” Playback EFM sync and interpolation protection timming much
62
RFCK
O
Read Frame Clock signal output
63
C2PO
–
Not used
64
XRAOF
O
Internal RAM overflow detection signal output (Not used)
65
MNT3
–
Not used
66
MNT1
–
Not used
67
MNT0
–
Not used
68
XTSL
–
Not used
69
FSTT
O
2/3 divider output (Not used)
70
C4M
O
4.2336MHz output(Not used)
71
DOUT
O
Digital audio signal output
72
EMPH
O
Playback disc output in emphasis mode
73
EMPHI
I
“H” =Input when de-emphasis ON
74
WFCK
O
Write Frame Clock signal output
75
SCOR
O
Sub-code sync output
76
SBSO
O
Sub-P through Sub-W serial output
77
EXCK
I
Clock input for SBSO read-out
78
VSS
–
Ground
79
VDD
–
+5V power supply
80
SYSM
I
System mute input (Connected to ground)
81
—
–
Not used
82
AVSS
–
Analog ground
83
AVDD
–
Analog power supply
84
AOUT1
O
Lch analog output
85
AIN1
I
Lch opamp input
86
LOUT1
O
Lch line output
87
AVSS
–
Analog ground
88
XVDD
–
Master clock power supply
89
XTAI
I
X’tal oscillator circuit input
90
XTAO
O
X’tal oscillator circuit output
– 10 –
Pin No.
Pin name
I/O
Description
1
GND
–
Ground.
2
RMIN
I
Remote control signal input.
3
GND
–
Ground.
4–7
NC
–
Not used (Open).
8
CLK
O
Serial clock output.
9
SENSE
I
Sense signal input from IC103 (CXD2529Q).
10
DATA
O
Serial data output.
11
SQCK
O
Sub Q clock output.
12
SUBQ
I
Sub Q data input.
13
SENSE2
I
Sense signal input from IC101 (CXA1992AR)
14
NC
–
Not used (Open).
15
XLT
O
Serial latch output.
16–19
NC
–
Not used (Open).
20
LD OUT
O
Loadin motor control.
21
LD IN
O
Loadin motor control.
22
KEY 0
I
Key input 0.
23
KEY1
I
Key input 1.
24–27
NC
–
Not used (Open).
28
ADJ/AFADJ
I
Test mode terminal.
29
IN/OUT SW
I
CD tray IN/OUT switch.
30
RST
I
System reset terminal.
31
EXTAL
O
System oscillator (4.0 MHz).
32
XTAL
I
System oscillator (4.0 MHz).
33
VSS
–
Ground.
34–41
NC
–
Not used (Open).
42–62
S21–S1
O
FL segment signal output.
63–67
1G–5G
O
FL grid signal output.
68
NC
–
Not used (Open).
69, 70
6G,7G
O
FL grid signal output.
71
VFDP
–
Pull down voltage (– 30V).
72
VDD
–
Power supply (+5V).
73,74
GND
–
Ground.
75
VDD
–
Power supply (+5V).
76,77
NC
–
Not used (Open).
78
SCOR
I
Sub code data request signal input.
79, 80
GND
–
Ground.
IC501 SYSTEM CONTROL (CXP82612-028Q)
Pin No.
Pin name
I/O
Description.
91
XVSS
–
Master clock ground
92
AVSS
–
Analog ground
93
LOUT2
O
Rch line output
94
AIN2
I
Rch opamp input
95
AOUT2
O
Rch analog output
96
AVDD
–
Analog power supply
97
AVSS
–
Analog ground
98
—
–
Not used
99
—
–
Not used
100
XRST
I
Sysyem reset input
– 16 –
1
5
2
6
3
7
4
r
WAVEFORMS
IC101
#£
RFO
IC101
$¶
TEI
IC103
^º
XPCK
IC101
2
FEI
IC103
(º
XTAO
IC103
@¶
MDP
IC103
^™
RFCK
1.1 Vp-p
20 mVp-p
7.5 µsec
16.9344 MHz
219 µsec
139.5 µsec
7 mVp-p
4.8 Vp-p
1.9 Vp-p
5 Vp-p
5.37 Vp-p
– 17 –
r
WAVEFORM
1
IC501
#™
XTAL
4 MHz
2 Vp-p
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