Sony CDP-M205 / CDP-M305 Service Manual ▷ View online
– 5 –
SECTION 3
DISASSEMBLY
Note
: Follow the disassembly procedure in the numerical order given.
3-1. PANEL, FRONT REMOVAL
2
5
5
6
Panel, Front
3
Wire (Flat type)
(21core)
Panel, Loading
3-2. CD MECHANISM SECTION REMOVAL
3
Wire (Flat type) (19 core)
2
4
CN151 (5P)
CD mechanism section
1
Three screws
(+BVTP 3x8 TYPE2 N-S)
Chassis assy
4
Two screws
(+BVTP 3x8TYPE2 N-S)
1
Turn in the direction
of the arrow
(Refer to page 4)
(Refer to page 4)
– 6 –
SECTION 4
ELECTRICAL ADJUSTMENTS
oscilloscope
BD board
TP (RF)
TP (VC)
TP (VC)
CD SECTION
Note:
1. CD Block is basically constructed to operate without adjustment.
Therefore, check each item in order given.
2. Use YEDS-18 disc (3-702-101-01) unless otherwise indicated.
3. Use an oscilloscope with more than 10M impedance.
4. Clean the object lens by an applicator with neutral detergent when
3. Use an oscilloscope with more than 10M impedance.
4. Clean the object lens by an applicator with neutral detergent when
the signal level is low than specified value with the following
checks.
checks.
S Curve Check
oscilloscope
BD board
TP (FEO)
TP (VC)
TP (VC)
Procedure :
1. Connect oscilloscope to test point TP (FEO).
2. Connect between test point TP (FOK) and Ground by lead wire.
3. Turn Power switch on.
4. Put disc (YEDS-18) in and turned Power switch on again and
1. Connect oscilloscope to test point TP (FEO).
2. Connect between test point TP (FOK) and Ground by lead wire.
3. Turn Power switch on.
4. Put disc (YEDS-18) in and turned Power switch on again and
actuate the focus search. (actuate the focus search when disc
table is moving in and out.)
table is moving in and out.)
5. Check the oscilloscope waveform (S-curve) is symmetrical be-
tween A and B. And confirm peak to peak level within 3 ± 1Vp-p.
S-curve waveform
within 3 ± 1 Vp-p
symmetry
B
A
6. After check, remove the lead wire connected in step 2.
Note:
• Try to measure several times to make sure than the ratio of
A : B or B : A is more than 10 : 7.
• Take sweep time as long as possible and light up the bright-
ness to obtain best waveform.
Procedure :
1. Connect oscilloscope to test point TP (RF) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in and playback.
4. Confirm that oscilloscope waveform is clear and check RF sig-
1. Connect oscilloscope to test point TP (RF) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in and playback.
4. Confirm that oscilloscope waveform is clear and check RF sig-
nal level is correct or not.
Note:
Clear RF signal waveform means that the shape “
◊
” can be
clearly distinguished at the center of the waveform.
RF signal waveform
VOLT/DIV: 200 mV
TIME/DIV: 500 nS
TIME/DIV: 500 nS
level: 1.1 ± 0.3 Vp-p
E-F Balance (1 Track Jump) check
oscilloscope
BD board
TP (TEO)
TP (VC)
TP (VC)
Procedure:
1. Connect oscilloscope to test point TP (TEO) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in to play the number five track.
4. Press the “
1. Connect oscilloscope to test point TP (TEO) on BD board.
2. Turned Power switch on.
3. Put disc (YEDS-18) in to play the number five track.
4. Press the “
P (Pause)” button.
5. Check the level B of the oscilloscope's waveform and the A (DC
voltage) of the center of the Traverse waveform.
Confirm the following:
Confirm the following:
• A/B x 100 = less than ± 7 (%)
1 track jump waveform
Center of the waveform
B
A (DC voitage)
Symmetry
level : 500 mV ± 100 mVp-p
Adjustment Location:
[BD BOARD] (Conductor Side)
CNU102
TP
(FOK)
(FOK)
TP
(RF)
(RF)
0V
IC102
IC101
IC103
TP
(TEO)
(TEO)
RF Level Check
TP
(VC)
TP
(FEO)
(FEO)
TP
(GND)
(GND)
CNU101
– 7 –
Pin No.
Pin name
I/O
Description.
1
FEO
O
Focus error amplifier output.
Connected internally to the window comparator input for bias adjustment.
2
FEI
I
Focus error input.
3
FDFCT
I
Capacitor connection pin for defect time constant.
4
FGD
I
Ground this pin through a capacitor for cutting the focus servo high-frequency gain.
5
FLB
I
External time constant setting pin for boosting the focus servo low-frequency.
6
FE O
O
Focus drive output.
7
FE M
I
Focus amplifier inverted input.
8
SRCH
I
External time constant setting pin for generating focus search waveform.
9
TGU
I
External time constant setting pin for switching tracking high-frequency gain.
10
TG2
I
External time constant setting pin for switching tracking high-frequency gain.
11
FSET
I
Peak frequency setting pin for focus and tracking phase compensation amplifier.
12
TA M
I
Tracking amplifier inverted input.
13
TA O
O
Tracking drive output.
14
SL P
I
Sled amplifier non-inverted input.
15
SL M
I
Sled amplifier inverted input.
16
SL O
O
Sled drive output.
17
ISET
I
Connect an external capacitance to set the current which determines the Focus search,
Track jump, and Sled kick heights.
18
VCC
I
Positive power supply.
19
LOCK
I
The sled overrun prevention circuit operates when this pin is Low (No pull-up resistance).
20
CLK
I
Serial data transfer clock input from CPU (No pull-up resistance).
21
XLT
I
Lach input from CPU (No pull-up resistance).
22
DATA
I
Serial data input from CPU (No pull-up resistance).
23
XRST
I
Reset input; resets at Low (No pull-up resistance).
24
C.OUT
O
Track number count signal output.
25
SENS1
O
Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the
command from CPU.
26
SENS2
O
Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from
CPU.
27
FOK
O
Focus OK comparator output.
28
CC2
I
Input for the defect bottom hold output with capacitance coupled.
29
CC1
O
Defect bottom hold output
Connected internally to the interruption comparator input.
30
CB
I
Connection pin for defect bottom hold capacitor.
31
CP
I
Connection pin for MIRR hold capacitor
MIRR comparator non-inverted input.
32
RF I
I
Input for the RF summing amplifier output with capacitance coupled.
33
RF O
O
RF summing amplifier output
Eye-pattern check point.
34
RF M
I
RF summing amplifier inverted input.
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin .
35
RFTC
I
External time constant setting pin during RF level control.
36
LD
O
APC amplifier output.
37
PD
I
APC amplifier input.
38
PD1
I
RF I-V amplifier inverted input.
39
PD2
I
Connect these pins to the photo diode A+C and B+D pins.
40
FE BIAS
I
Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment (not used).
SECTION 5
DIAGRAMS
5-1. IC PIN FUNCTION
IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR)
– 8 –
Pin No.
Pin name
I/O
Description.
1
VDD
–
+5V power supply
2
VSS
–
Ground
3
LMUT
O
Lch “L” detection flog (Not used)
4
RMUT
O
Rch “L” detection flog (Not used)
5
ACDT
O
Test output (Not used)
6
CKOUT
O
Master clock divider output (Not used)
7
SQCK
I
Clock input for SQSO read out
8
SQSO
O
Serial output for Sub-Q 80bit
9
SENS
O
SENS signal output to CPU
10
DATA
I
Serial data input, supplied from CPU
11
XLAT
I
Latch input, supplied from CPU
12
CLOK
I
Serial data transfer clock input, supplied from CPU
13
SEIN
I
SENS input from IC101
14
CNIN
I
Numbers of track jump counted signal input
15
DATO
O
Serial data output to IC101
16
XLTO
O
Serial data latch output to IC101
17
CLKO
O
Serial data transfer clock output to IC101
18
SPOA
I
Micro computer demodulation interface (Input A)
19
SPOB
I
Micro computer demodulation interface (Input B)
20
SPOC
I
Micro computer demodulation interface (Input C)
21
SPOD
I
Micro computer demodulation interface (Input D)
22
XLON
O
Micro computer demodulation interface (Output) (not used)
23
FOK
I
Focus OK input
24
VDD
–
+5V power supply
25
VSS
–
Ground
26
MON
O
Output to control ON/OFF of spindle motor (Not used)
27
MDP
O
Output to control spindle motor servo
28
MDS
O
Output to control spindle motor servo (Not used)
29
LOCK
O
GFS is sampled by 460Hz
30
PWMI
I
Input to control the outside spindle motor
31
TES0
I
Test pin (Connected to ground)
32
TES1
I
Test pin (Connected to ground)
33
VPCO2
O
Charge-pump output (Not used)
34
VPCO1
O
Charge-pump output (Not used)
35
VCKI
I
VCO2 oscillator input (Not used)
36
V16M
O
VCO2 oscillator output (Not used)
Pin No.
Pin name
I/O
Description.
41
F
I
F I-V and E I-V amplifier inverted input.
42
E
I
Connect these pins to photo diodes F and E.
43
EI
–
I-V amplifier E gain adjustment
(When not using automatic balance adjustment) (not used).
44
VEE
–
Negative power supply.
45
TEO
O
Tracking error amplifier output
E-F signal is output.
46
LPFI
I
Comparator input for balance adjustment
(Input from TEO through LPF).
47
TEI
I
Tracking error input.
48
ATSC
I
Window comparator input for ATSC detection.
49
TZC
I
Trackig zero-cross comparator input.
50
TDFCT
I
Capacitor connection pin for defect time constant.
51
VC
O
(VCC + VEE)/2 direct voltage output.
52
FZC
I
Focus zero-cross comparator input.
IC103 DIGITAL SIGNAL PROCESSOR (CXD2529Q)
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