Sony CDP-CX270 / CDP-CX90ES Service Manual ▷ View online
— 33 —
Pin Name
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
GTOP
XUGF
XPLCK
GFS
PFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DVss
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
–
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
–
I
O
O
O
I
O
O
O
O
O
I
O
I
I
O
Function
Digital power supply
Asymmetry circuit ON/OFF (Connected to +5V)
Audio data output mode selection input (Connected to Ground)
48-bit slot D/A interface. Word clock. (Open)
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1. 48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1. 48-bit slot data when PSSL=0
DA 14 output when PSSL=1. 64-bit slot data when PSSL=0 (Open)
DA 13 output when PSSL=1. 64-bit slot data when PSSL=0 (Open)
DA 12 output when PSSL=1. 64-bit slot data when PSSL=0 (Open)
DA 11 output when PSSL=1. GTOP output when PSSL=0 (Open)
DA 10 output when PSSL=1. XUGF output when PSSL=0 (Open)
DA 09 output when PSSL=1. XPLCK output when PSSL=0 (Open)
DA 08 output when PSSL=1. GFS output when PSSL=0 (Open)
DA 07 output when PSSL=1. RFCK output when PSSL=0 (Open)
DA 06 output when PSSL=1. C2PO output when PSSL=0 (Open)
DA 05 output when PSSL=1. XRA0F output when PSSL=0 (Open)
DA 04 output when PSSL=1. MNT3 output when PSSL=0 (Open)
DA 03 output when PSSL=1. MNT2 output when PSSL=0 (Open)
DA 02 output when PSSL=1. MNT1 output when PSSL=0 (Open)
DA 01 output when PSSL=1. MNT0 output when PSSL=0 (Open)
X'tal oscillator circuit input
X'tal oscillator circuit output (Open)
X'tal selection input pin (Connected to Ground)
Digital Ground
Clock input for digital servo block
2/3 divider output of pins 62, 63
1/4 divider output of pins 62, 63 (Open)
16.9344 MHz output (Open)
Digital-out ON/OFF control pin (Connected to +5V)
Digital-out output pin
Playback disc output in emphasis mode (Open)
WFCK output
Sub-code sync output
Sub-P through Sub-W serial output
Clock input for SBSO read-out
Sub-Q 80-bit output
Clock input for SQSO read-out
Muting selection pin
SENS output
• Abbreviation
WFCK: Wirte Frame Clock
— 34 —
Pin Name
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DVDD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
Pin No.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I
I
I
I
I
I
I
I
O
–
O
O
O
O
O
O
O
O
I
O
• Abbreviation
GFS: Guard Frame Sync
Function
System reset
Used in 1-track jump mode (Connected to +5v)
SENS serial data read-out clock
Defect selection pin (Connected to Ground)
Input pin for anti-shock (Connected to Ground)
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
Numbers of track counted signal output (Open)
Digital power supply
Mirror signal output (Open)
Defect signal output (Open)
Focus OK output (Open)
Output to select spindle motor output filter (Open)
Output to control ON/OFF of spindle motor (Open)
Output to control spindle motor servo
Output to control spindle motor servo (Open)
GFS is sampled by 460 Hz. H when GFS is H (Open)
Input signal to detect disc inner most track
Sled drive output
— 35 —
• IC401 SYSTEM CONTROL (MB90677)
Pin Name
A16
A17
CE1
CE2
ADJ
AF ADJ
––
––
ALE
OE
DGND
WE
––
SPDT
CLK-T
XMODE
XLT
K. DATA-I
K. DATA-O
K. CLK-O
––
DATA
DVDD
CLK
TBLL
AMUTE
TBLR
––
PGM. LT
LDON
SENSE
SUBQ
SQCK
AVCC
AVR +
AVR –
AVss
KEY0
KEY1
KEY2
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
O
O
O
O
I
I
O
O
O
O
–
I
O
I
O
O
O
I
O
O
O
O
–
O
O
O
O
O
O
O
I
I
O
–
–
–
–
I
I
I
Function
Address terminal for external RAM/ROM
Chip select
Chip select
Chip select
ADJ mode input pin
AFADJ mode input pin
Open
Open
Address latch enable
Lower during read
Digital ground
Write signal of data bus low order 8 bit
Open
Data input from IC for CD-TEXT (LC89170M)
Clock output to IC for CD-TEXT (LC89170M)
Reset output to IC for CD-TEXT (LC89170M)
Latch output to CXD2545
Keyboard data input
Keyboard data output
Keyboard clock output
Connected to Ground
Data output for D/F pin of CXD2545
5V power supply
5V power supply clock output
Table motor output for left tern
Audio mute output
Table motor output for right tern
Open
Latch output
Laser diode on
Sense input from CXD2545
Sub code Q data input
Sub code Q data read-out clock
Analog power supply (Connected to +5V)
Analog reference voltage input (Connected to +5V)
Analog reference voltage input (Connected to ground)
Analog ground
Key input
Key input
Key input
— 36 —
I/O
I
–
I
I
I
I
–
–
–
–
I
I
I
I
I
I
I
I
I
O
O
O
O
I
I
O
O
O
O
O
O
I
I
O
O
I
O
I
I
Function
Key input
Ground pin
Command mode switch
Fluorescent indicator tube select port for different destination
Table driver
Disc sensor input
Open port
Micro computer mode
Micro computer mode
Micro computer mode
Hardware stand-by input
SCOR input from CXD2545
Table sensor input
Table sensor input
CD-TEXT sync input
Keyboard clock input
Remote control signal input
Table sensor
Control A1 input
Control A1 output
Open port
Open port
Open port
BU up switch input
BU down switch input
Microprocessor peripheral IC power supply
Loading motor output for outside direction
Loading motor output for inside direction
Chip select output for OSD IC (MB90095)
Open port
Open port
Timer switch input
Tray close switch input
Chip select input for LED driver
Chip select output for fluorescent indicator tube driver (IC1 M66004M5SP)
Reset input
Chip select output for fluorescent indicator tube driver (IC2 M66004M5SP)
Jog dial input
Jog dial input
Pin Name
KEY3
VSS
CD1/2/3
FL. SLCT
T. DRV
D. SENS
L. NTSC
H. PAL
––
M2
M1
M0
HSTX
SCOR
T. SENS 2
T. SENS 1
DQSY
K. CLKI
RMIN
T. SENS 3
BUS IN
BUS OUT
––
––
––
DOWN SW
UP SW
POWER
LOD OUT
LOD IN
OSD. CS
––
––
TIMER
DOOR-SW
LED LT
FL-T 2
RESET
FLT 1
JOG 2
FOG 1
Pin No.
41
42
43
44
45
46
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
47
I
NTSC/PAL select
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