DOWNLOAD Sony CDP-CE275 / CDP-CE375 Service Manual ↓ Size: 2.95 MB | Pages: 41 in PDF or view online for FREE

Model
CDP-CE275 CDP-CE375
Pages
41
Size
2.95 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
cdp-ce275-cdp-ce375.pdf
Date

Sony CDP-CE275 / CDP-CE375 Service Manual ▷ View online

25
CDP-CE275/CE375
– BD Board –
IC131
CXA2581N
10
11
12
4
3
EQ IN
9
D
10
F
E
8
C
7
B
6
A
AC SUM
DC_OFST
RFDCI
11 RFDCO
VC
24 BST
25 VFC
CEI
EQ
APC
5
GND
AC
SUM
26 RFC
AC
VCA
23 RFG
22 VCC
20
21
CE
19 TE_BAL
18 TE
17 FEI
16 FE
1
LD
2
PD
11
SW 12
13
DVCC
14
DVC
15
RFAC
VC
EQ
ON/OFF
VC
VC
VC
VC
DVC
DVC
APC-OFF(Hi-Z)
RW/ROM
(H/L)
DVC
DVC
AVC
DVCC
VC
DVC
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
DVCC
VCC
VCC
VCC
VOFST
VOFST
VOFST
B
C
A
D
gm
gm
DVCC
– JUNCTION Board –
IC11
BA6780
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER 
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
26
CDP-CE275/CE375
6-10.
IC  PIN  FUNCTION  DESCRIPTION
• BD BOARD  IC101  CXD2587Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
SQSO
O
Subcode Q data output to the system controller (IC301)
2
SQCK
I
Subcode Q data reading clock signal input from the system controller (IC301)
3
XRST
I
System reset signal input from the system controller (IC301)    “L”: reset
4
SYSM
I
Analog line muting on/off control signal input terminal    “H”: line muting on
Not used (fixed at  “L”)
5
DATA
I
Command serial data input from the system controller (IC301)
6
XLAT
I
Command latch pulse input from the system controller (IC301)
7
CLOK
I
Command serial data transfer clock signal input from the system controller (IC301)
8
SENS
O
Internal status monitor output to the system controller (IC301)
9
SCLK
I
SENSE serial data reading clock input from the system controller (IC301)
10
VDD
Power supply terminal (+5V) (digital system)
11
ATSK
I/O
Input pin for anti-shock    Not used (fixed at  “L”)
12
SPOA
I
Microcomputer escape interface input A terminal    Not used (fixed at  “L”)
13
SPOB
I
Microcomputer escape interface input B terminal    Not used (fixed at  “L”)
14
XLON
O
Microcomputer escape interface output to the CXA2568M (IC103)
15
WFCK
O
WFCK output terminal     Not used (open)
16
XUGF
O
Not used (open)
17
XPCK
O
Not used (open)
18
GFS
O
Not used (open)
19
C2PO
O
Not used (open)
20
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC301)
21
COUT
I/O
Numbers of track counted signal input/output terminal    Not used (open)
22
MIRR
I/O
Mirror signal input/output terminal    Not used (open)
23
DFCT
I/O
Defect signal input/output terminal    Not used (open)
24
FOK
I/O
Focus OK input/output terminal    Not used (open)
25
LOCK
I/O
GFS is sampled by 460 Hz    “H” when GFS is “H”    Not used (open)
26
MDP
O
Spindle motor (M101) servo drive signal output to the BA5974FP (IC102)
27
SSTP
I
Limit in detect switch (S101) input terminal
28
SFDR
O
Sled servo drive PWM signal (+) output to the BA5974FP (IC102)
29
SRDR
O
Sled servo drive PWM signal (–) output to the BA5974FP (IC102)
30
TFDR
O
Tracking servo drive PWM signal (+) output to the BA5974FP (IC102)
31
TRDR
O
Tracking servo drive PWM signal (–) output to the BA5974FP (IC102)
32
FFDR
O
Focus servo drive PWM signal (+) output to the BA5974FP (IC102)
33
FRDR
O
Focus servo drive PWM signal (–) output to the BA5974FP (IC102)
34
VSS
Ground terminal (digital system)
35
TEST
I
Input terminal for the test (fixed at “L”)
36
TES1
I
Input terminal for the test (fixed at “L”)
37
XTSL
I
Input terminal for the system clock frequency setting    “L”: 45.1584 MHz, “H”: 22.5792 MHz
(fixed at “L” in this set)
38
VC
I
Middle point  voltage (+2.5V) input from the CXA2568M (IC103)
39
FE
I
Focus error signal input from the CXA2568M (IC103)
40
SE
I
Sled error signal input from the CXA2568M (IC103)
41
TE
I
Tracking error signal input from the CXA2568M (IC103)
42
CE
I
Command chip enable signal input from the CXA2568M (IC103)
27
CDP-CE275/CE375
Pin No.
Pin Name
I/O
Description
43
RFDC
I
RF signal input from the CXA2568M (IC103)
44
ADIO
O
Monitor output of the A/D converter input signal    Not used (open)
45
AVSS0
Ground terminal (digital system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
Power supply terminal (+5V) (digital system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
51
RFAC
I
EFM signal input from the CXA2568M (IC103)
52
AVSS3
Ground terminal (digital system)
53
CLTV
I
Internal VCO control voltage input of the playback master PLL
54
FILO
O
Filter output for master clock of the playback master PLL
55
FILI
I
Filter input for master clock of the playback master PLL
56
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
57
AVDD3
Power supply terminal (+5V) (digital system)
58
VSS
Ground terminal (digital system)
59
VDD
Power supply terminal (+5V) (digital system)
60
DOUT
O
Digital audio signal output to the DIGITAL OUT OPTICAL (IC303)
61
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal    Not used (open)
62
PCMD
O
D/A interface serial data output terminal    Not used (open)
63
BCK
O
Bit clock signal (2.8224 MHz) output terminal    Not used (open)
64
EMPH
O
De-emphasis control signal output terminal    Not used (open)
65
XVDD
Power supply terminal (+5V) (crystal oscillator system)
66
XTAI
I
System clock input terminal (16.9344 MHz)
67
XTAO
O
System clock output terminal (16.9344 MHz)
68
XVSS
Ground terminal (crystal oscillator system)
69
AVDD1
Power supply terminal (+5V) (analog system)
70
AOUT1
O
L-ch analog audio signal output terminal
71
AIN1
I
L-ch operational amplifiers input terminal
72
LOUT1
O
L-ch line output terminal
73
AVSS1
Ground terminal (analog system)
74
AVSS2
Ground terminal (analog system)
75
LOUT2
O
R-ch line output terminal
76
AIN2
I
R-ch operational amplifiers input terminal
77
AOUT2
O
R-ch analog audio signal output terminal
78
AVDD2
Power supply terminal (+5V) (analog system)
79
RMUT
O
R-ch line muting on/off control signal output terminal
80
LMUT
O
L-ch line muting on/off control signal output terminal
28
CDP-CE275/CE375
• MAIN BOARD  IC301  CXP82532-013Q
(SYSTEM CONTROLLER, FLUORESCENT INDICATOR TUBE DRIVER, KEY CONTROL)
Pin No.
Pin Name
I/O
Description
1
BUSIN
I
Sircs remote control signal input terminal    Not used (pull up)
2
RMIN
I
Remote control signal input from the remote control receiver (IC802)
3
NC
I
Not used (open)
4
XLT
O
Serial data latch pulse signal output to the CXD2587Q (IC101)
5
LDON
O
Laser diode ON/OFF output
6
TSENS
I/O
Detect signal input from the table sensor (D10)
7
DA CS
I/O
DA CS
8
CLK
I/O
Serial data transfer clock signal output to the CXD2587Q (IC101)
9
LDON/RW
I/O
Laser diode ON/OFF output
10
DATA
I/O
Serial data output to the CXD2587Q (IC101)
11
SQCK
I/O
Sub-code Q data reading clock signal output to the CXD2587Q (IC101)
12
SUBQ
I/O
Sub-code Q data signal input from the CXD2587Q (IC101)
13
NC
O
Not used (open)
14
OUT SW
I/O
Detect signal input from the open/close detect switch (S11)
15
S1
I/O
Detect signal input from the tray address detect switch (S200)
16
S2
I/O
Detect signal input from the tray address detect switch (S200)
17
NC
I/O
Not used (open)
18
TBLL
I/O
Table motor drive signal (counterclockwise) output to the BA6780 (IC11)
19
TBLR
I/O
Table motor drive signal (clockwise) output to the BA6780 (IC11)
20
LD IN
I/O
Loading motor (M11) drive signal output to the BA6780 (IC11)    *1
21
LD OUT
I/O
Loading motor (M11) drive signal output to the BA6780 (IC11)    *1
22
NC
I/O
Not used (open)
23
NC
I/O
Not used (open)
24
TEST
I/O
Key input terminal (A/D input)
25
KEY3
I/O
Key input terminal (A/D input) (S812 to S816)
26
KEY4
I/O
Key input terminal (A/D input) (S817 to S821)
27
KEY5
I/O
Key input terminal (A/D input) (S806 to S810)
28
KEY6
I/O
Key input terminal (A/D input) (S801 to S805)
29
NC
I/O
Not used (open)
30
RST
I/O
System reset signal input from the reset signal generator (IC601)    “L”:reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (10 MHz)
32
XTAL
O
Main system clock output terminal (10 MHz)
33
VSS
Ground terminal
34
NC
O
Not used (open)
35
NC
O
Not used (open)
36
NC
O
Not used (open)
37
NC
O
Not used (open)
*1   Loading motor (M11) control
Operation
OFF
OFF
IN BRAKE
Terminal
LOAD IN (pin @º)
“L”
“L”
“H”
“H”
LOAD OUT (pin @¡)
“L”
“H”
“L”
“H”
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