Sony CDP-CA70ES Service Manual ▷ View online
— 39 —
IC802 LC75721E (DISPLAY BOARD)
64
63
62
60
58
55
61
56
59
58
39
36
35
37
38
40
41
42
43
44
45
53
54
1
2
CONTROL
SHIFT
REGISTER
DI
CL
CE
VDD
VSS
VFL
RES
TEST
DC RAM
ADDRESS
RESISTOR
BLINKCYCLE
RESISTOR
DISPLAY
RESISTOR
DUTYCYCLE
RESISTOR
GLID
RESITOR
INSTRUCTION
RESISTOR
TIMING
GENERATOR
ADDRESS
COUNTER
BLINK
GENERATOR
DISPLAY
CONTROL
DUTY
GENERATOR
GLID
CONTROL
CONTROL
LA
TCH
LA
TCH
ANODE DRIVER
CG ROM
CG RAM
AD RAM
DECODER
GRID DRIVER
DRIVER
OSC
OSC1
OSC2
G1
G2
G10
G11
N.C.
N.C.
41
P39
P40
P38
P36
P35
P2
P1
P37
— 40 —
6-13. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2585Q) (BD BOARD)
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2585Q) (BD BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
DVDD
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
CM4
WDCK
DVSS
COUT
MIRR
DFCT
FOK
PWMI
LOCK
MDP
SSTP
FSTO
DVDD1
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DVSS1
TEST
TES1
VC
FE
SE
I/O
—
I
I
I
I
I
O
I
I/O
O
O
O
O
O
O
O
O
—
I/O
I/O
I/O
I/O
I
I/O
O
I
O
—
O
O
O
O
O
O
—
I
I
I
I
I
Function
Digital power supply
System reset
“L” : reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Input pin for anti-shock (Connected to ground)
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
4.2336 MHz output (Not used)
Word clock output (ƒ = 2Fs)
Digital ground
Numbers of track counted signal input/output (Not used)
Mirror signal input/output
Defect signal input/output
Focus OK input/output
Spindle motor external control input (Connected to ground)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor servo
Input signal to detect disc inner most track
2/3 divider output of pin 71
Digital power supply
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Center voltage input pin
Focus error signal input
Sled error signal input
• Abbreviation
GFS : Guarded Frame Sync
— 41 —
• Abbreviation
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
PLL : Phase Locked Loop
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
TE
CE
RFDC
ADIO
AVSS0
IGEN
AVDD0
ASYO
ASYI
RFAC
AVSS1
CLTV
FILO
FILI
PCO
AVDD1
BIAS
VCTL
V16M
VPCO
DVDD2
ASYE
MD2
DOUT
LRCK
PCMD
BCLK
EMPH
XTSL
DVSS2
XTAI
XTAO
SOUT
SOCK
XOLT
SQSO
SQCK
SCSY
SBSO
EXCK
I/O
I
I
I
O
—
I
—
O
I
I
—
I
O
I
O
—
I
I
I/O
O
—
I
I
O
O
O
O
O
I
—
I
O
O
O
O
O
I
I
O
I
Function
Tracking error signal input
Center servo analog input
RF signal input
Test pin (Not used)
Analog ground
Stabilized current input for operational amplifiers
Analog power supply
EFM full swing output
Asymmetry comparate voltage input
EFM signal input
Analog ground
Control voltage input for master VCO1
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Analog power supply
Asymmetry circuit constant current input
VCO2 control voltage input for wide band EFM PLL (Connected to VDD)
VCO2 oscillator input/output for wide band EFM PLL (Not used)
Charge-pump output for wide band EFM PLL (Not used)
Digital power supply
Asymmetry circuit ON/OFF input
“L” OFF, “H” : ON (Connected to VDD)
Digital-out ON/OFF control input (Connected to VDD)
Digital-out output pin
D/A interface LR clock output (ƒ = Fs)
D/A interface serial data output
D/A interface bit clock output
Playback disc output in emphasis mode (Not used)
X'tal selection input (Connected to ground)
Digital ground
X'tal oscillator circuit input
X'tal oscillator circuit output (Not used)
Serial data output in servo block (Not used)
Serial data read clock output in servo block (Not used)
Serial data latch output in servo block (Not used)
Sub-Q 80-bit and PCM peak level data output (CD text data output)
Clock input for SQSO read-out
Connected to ground
Sub-P through Sub-W serial output (Not used)
Clock input for SBSO read-out (Connected to ground)
— 42 —
I/O
O
O
O
O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
—
—
—
O
I
O
O
O
O
O
O
O
I
—
I
—
—
—
—
—
—
—
O
—
I
• IC501 SYSTEM CONTROL (CXP84648-052Q) (MAIN BOARD)
Pin Name
A5
A4
A3
A2
NC
D0
D1
D2
D3
D4
D5
D6
D7
PLAY_L
PAUSE_L
LED MEGA
LED XFADE
LED DELAY
WE
LODIN
LODOUT
FLCLK
FLDATA
BLK
A1
A0
A13
D_SENS
NC
RESET
10MHz
10MHz
GND
NC
TEX
AVSS
AVREF
BUSOUT
VERSION
KEY2
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Function
SRAM address 5
SRAM address 4
SRAM address 3
SRAM address 2
Not used
SRAM data 0
SRAM data 1
SRAM data 2
SRAM data 3
SRAM data 4
SRAM data 5
SRAM data 6
SRAM data 7
PLAY lamp
PAUSE lamp
Not used
Not used
Not used
SRAM enable
Loading direction signal input
Loading direction signal output
Display clock
Display data
Display reset
SRAM address 1
SRAM address 0
SRAM address 13
Disc exist/non-exist sensor
Not used
Microprocessor reset
Ceramic oscillator
Ceramic oscillator
Ground (0V)
Not used
Ground (0V)
Ground (0V)
Reference voltage for AV converter. Fixed to VDD
Control A1 output
Ground (0V)
Key input 2
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