Sony BDV-L600 / BDV-L800 / BDV-L800M / HBD-L600 / HBD-L800 / HBD-L800M Service Manual ▷ View online
HBD-L600/L800/L800M
81
Pin No.
Pin Name
I/O
Description
AF11,
AF12
RDQ30, RDQ20
I/O
Two-way data bus with the SD-RAM
AF13,
AF14
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF15,
AF16
RA9, RA2
O
Address signal output to the SD-RAM
AF17
DGND
-
Ground terminal
AF18,
AF19
RDQ1, RDQ3
I/O
Two-way data bus with the SD-RAM
AF20
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF21 to
AF23
RDQ15, RDQ6,
RDQ5
I/O
Two-way data bus with the SD-RAM
AF24
TN_MEMPLL
-
Test terminal
AF25
RDQ16_B
I/O
Two-way data bus with the SD-RAM
AF26
DGND
-
Ground terminal
AF27
RDQS3_B_
O
Data strobe signal (negative) output to the SD-RAM
AF28
RDQS3_B
O
Data strobe signal (positive) output to the SD-RAM
AG1,
AG2
NFD3, NFD0
I/O
Two-way data bus with the NAND fl ash
AG3
NFCLE
O
Command latch enable signal output to the NAND fl ash
AG4
NFWEN
O
Write enable signal output to the NAND fl ash
AG5
SFDI
O
LPF selection signal output terminal Not used “L”: 13.5 MHz LPF, “H”: 30 MHz LPF
AG7,
AG8
RDQ16, RDQ19
I/O
Two-way data bus with the SD-RAM
AG9
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG10
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG11
RDQ29
I/O
Two-way data bus with the SD-RAM
AG13
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG14
RBA0
O
Bank address signal output to the SD-RAM
AG16
RCKE
O
Clock enable signal output to the SD-RAM
AG17
RDQ0
I/O
Two-way data bus with the SD-RAM
AG19
RDQ9
I/O
Two-way data bus with the SD-RAM
AG20
RDQS0
O
Data strobe signal (positive) output to the SD-RAM
AG21
RDQS1_
O
Data strobe signal (negative) output to the SD-RAM
AG22
RDQ7
I/O
Two-way data bus with the SD-RAM
AG24
RCLK0
O
Clock signal (positive) output to the SD-RAM
AG25
RDQ17_B
I/O
Two-way data bus with the SD-RAM
AG26
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AG27
RDQS2_B
O
Data strobe signal (positive) output to the SD-RAM
AG28
RDQS2_B_
O
Data strobe signal (negative) output to the SD-RAM
AH1
NFD1
I/O
Two-way data bus with the NAND fl ash
AH2
NFCEN
O
Chip enable signal output to the NAND fl ash
AH4
SFDO
O
Serial data output terminal Not used
AH5
SFCS
O
USB VBUS on/off control signal output terminal wireless LAN card “H”: VBUS on
AH7,
AH8
RDQ17, RDQ18
I/O
Two-way data bus with the SD-RAM
AH9
RDQS2_
O
Data strobe signal (negative) output to the SD-RAM
AH10
RDQS3
O
Data strobe signal (positive) output to the SD-RAM
AH11
RDQ28
I/O
Two-way data bus with the SD-RAM
AH13
RCLK1_
O
Clock signal (negative) output to the SD-RAM
AH14
RA3
O
Address signal output to the SD-RAM
AH16,
AH17
RA8, RA10
O
Address signal output to the SD-RAM
AH19
RDQ8
I/O
Two-way data bus with the SD-RAM
AH20
RDQS0_
O
Data strobe signal (negative) output to the SD-RAM
AH21
RDQS1
O
Data strobe signal (positive) output to the SD-RAM
AH22
RDQ13
I/O
Two-way data bus with the SD-RAM
AH24
RCLK0_
O
Clock signal (negative) output to the SD-RAM
AH25 to
AH28
RDQ18_B, RDQ19_B,
RDQ26_B, RDQ27_B
I/O
Two-way data bus with the SD-RAM
HBD-L600/L800/L800M
82
MB-141 BOARD IC6201 R5F3650KBDFA (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
BD_SDI
O
Serial data output to the BD decoder
2
BD_SCLK
I
Serial data transfer clock signal input from the BD decoder
3
SIRCS_IN2
I
SIRCS signal input from the remote control receiver
4
SIRCS_IN
I
SIRCS signal input from the remote control receiver
5
FL_DOUT
O
Serial data output to the fl uorescent indicator tube driver
6
S-AIR_GPIO2
I
Interrupt signal input from the wireless transceiver (EZW-RT50)
7
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube driver
8
BYTE
I
External data bus width selection signal input terminal
9
CNVss
I
Processor mode selection signal input terminal
10
ADC_PDN
O
Power down signal output terminal Not used
11
NO USE
O
Not used
12
RESET
I
System reset signal input from the reset switch “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
13
Xout
O
System clock output terminal (8 MHz)
14
Vss
-
Ground terminal
15
Xin
I
System clock input terminal (8 MHz)
16
Vcc
-
Power supply terminal (+3.3V)
17
CEC (TX/RX)
I/O
CEC serial data input/output with the HDMI connector
18
TS_INT
I
Interrupt signal input from the touch sensor driver
19
KEY_INT
I
Key wake-up signal input terminal
20
AC_CUT
I
AC cut detection signal input terminal “L”: AC cut
21
BD_IF_START
O
Ready signal output to the BD decoder “H”: ready
22
LED_PWM3
O
LED drive signal output terminal (HBD-L600 only)
23
TS_RST
O
Reset signal output to the touch sensor driver “L”: reset
24
PCONT_TS
O
Power supply on/off control signal output terminal for touch sensor “H”: power on
25
BD_IF_REQ
I
Request signal input from the BD decoder
26
LED_PWM2
O
LED drive signal output terminal
27
PCONT_FL
O
Power supply on/off control signal output terminal for fl uorescent indicator tube driver
“H”: power on
“H”: power on
28
LED_PWM1
O
LED drive signal output terminal
29
S-AIR_SCL
I/O
Two-way I2C clock bus with the wireless transceiver (EZW-RT50)
30
S-AIR_SDA
I/O
Two-way I2C data bus with the wireless transceiver (EZW-RT50)
31
TXD1
O
Not used
32
RXD1
I
Not used
33
CLK1
O
Not used
34
RTS1
O
Not used
35
HAMON_RXD
O
Serial data output to the LED controller (HBD-L800/L800M only)
36
HAMON_TXD
I
Serial data input from the LED controller (HBD-L800/L800M only)
37
NO USE
O
Not used
38
PCONT_CORE
O
Power supply on/off control signal output terminal “H”: power on
39
PCONT2
O
Power supply control signal output terminal Not used
40
PCONT3
O
Power supply on/off control signal output terminal “H”: power on
41
PCONT4
O
Power supply control signal output terminal Not used
42
HDMI_PCONT
O
Power supply control signal output terminal Not used
43
ATA_PCONT1
O
Power supply on/off control signal output terminal “H”: power on
44
FAN_ON
O
Power supply on/off control signal output terminal for fan motor “H”: power on
45
FAN_CONT
O
Fan motor on/off control signal output terminal “H”: motor on
46
CE
I
Chip enable signal input terminal Not used
47
ST_SDA
I/O
Two-way data bus with the FM receiver
48
ST_SCL
O
Serial data transfer clock signal output to the FM receiver
49
NO USE
O
Not used
50
PCONT_REG
O
Power supply on/off control signal output terminal
51 to 55
NO USE
-
Not used
56
HAMON_MODE
O
Mode setting signal output to the LED controller (HBD-L800/L800M only)
57
HAMON_RST
O
Reset signal output to the LED controller (HBD-L800/L800M only)
58
FAN_DET
I
Not used
59 to 61
NO USE
-
Not used
62
Vcc
-
Power supply terminal (+3.3V)
63
S-AIR_RST
O
Reset signal output to the digital sample rate converter and wireless transceiver (EZW-RT50)
HBD-L600/L800/L800M
83
Pin No.
Pin Name
I/O
Description
64
Vss
-
Ground terminal
65
NO USE
I
Not used
66
S-AIR_RF_FB
I
RF feedback signal output terminal Not used
67, 68
NO USE
-
Not used
69
FE_RST_IF
O
Reset signal output terminal Not used
70
FL_CS
O
Chip select signal output to the fl uorescent indicator tube driver
71 to 74
NO USE
O
Not used
75
ST_RDS_INT
I
RDS interrupt signal input from the FM receiver
76
NO USE
O
Not used
77
TS_SDA
I/O
Two-way data bus with the touch sensor driver
78
TS_SCL
I/O
Two-way clock bus with the touch sensor driver
79
ATA_PCONT2
O
Power supply control signal output terminal Not used
80
NO USE
O
Not used
81
SRS_INT
O
Reset signal output terminal Not used
82
PCONT1
O
Power supply on/off control signal output terminal “H”: power on
83
BD_RESET
O
Reset signal output to the BD decoder, NAND fl ash and EEPROM “L”: reset
84
JIG_MODE1
I
Jig mode selection signal input from the BD decoder
85
OPWRSB
I
Power control signal input from the BD decoder
86
FE_EJECT
O
Eject/stop key input detection signal output to the BD decoder
87
UPG_STATUS
I
UPG status signal input from the BD decoder
88
BD_CS
O
Chip select signal output to the BD decoder
89
NO USE
I
Not used
90
S-AIR_DET
I
Wireless transceiver detection signal input from the wireless transceiver (EZW-RT50)
91
BD_TEMP
I
Temperature detection signal input terminal
92
DESTINATION
I
Destination setting terminal
93
MODEL
I
Model setting terminal Fixed at “L” in this unit
94, 95
KEY2, KEY1
I
Key input terminal Not used
96
Vss
-
Ground terminal
97
KEY0
I
Power supply key input terminal
98
Vref
I
Reference voltage (+3.3V) input terminal
99
Vcc
-
Power supply terminal (+3.3V)
100
BD_SDO
I
Serial data input from the BD decoder
HBD-L600/L800/L800M
84
HAMON LED BOARD IC801 R5F21248SNFP (LED CONTROLLER) (HBD-L800/L800M only)
Pin No.
Pin Name
I/O
Description
1
NO USE
-
Not used
2 to 4
LED_10, LED_04,
LED_03
O
LED drive signal output terminal for illumination
5
MODE
I
Mode setting signal input from the system controller
6, 7
LED_02, LED_01
O
LED drive signal output terminal for illumination
8
RESET
O
Reset signal input from the system controller
9
Xout
O
System clock output terminal (20 MHz)
10
Vss
-
Ground terminal
11
Xin
I
System clock input terminal (20 MHz)
12
VCC
-
Power supply terminal (+3.3V)
13 to 17
NO USE
-
Not used
18 to 20
LED_17 to LED_15
O
LED drive signal output terminal for illumination
21, 22
NO USE
-
Not used
23 to 25
LED_14, LED_13,
LED_11
O
LED drive signal output terminal for illumination
26, 27
NO USE
-
Not used
28
HAMON_TXD
O
Serial data output to the system controller
29
HAMON_RXD
I
Serial data input from the system controller
30 to 38
LED_12,
LED_18 to LED_25
O
LED drive signal output terminal for illumination
39, 40
NO USE
-
Not used
41
SPEANA
I
Spectrum analyzer drive signal input from the D/A converter
42, 43
NO USE
-
Not used
44
Vref
I
Reference voltage (+3.3V) input terminal
45 to 47
NO USE
-
Not used
48 to 52
LED_09 to LED_05
O
LED drive signal output terminal for illumination
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