Sony BDV-E280 / BDV-T28 / HBD-E280 / HBD-T28 Service Manual ▷ View online
HBD-E280/T28
73
Pin No.
Pin Name
I/O
Description
AF8, AF9
RDQ25, RDQ27
I/O
Two-way data bus with the SD-RAM
AF10
DGND
-
Ground terminal
AF11,
AF12
RDQ30, RDQ20
I/O
Two-way data bus with the SD-RAM
AF13,
AF14
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF15,
AF16
RA9, RA2
O
Address signal output to the SD-RAM
AF17
DGND
-
Ground terminal
AF18,
AF19
RDQ1, RDQ3
I/O
Two-way data bus with the SD-RAM
AF20
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AF21,
AF22
RDQ15, RDQ6
I/O
Two-way data bus with the SD-RAM
AF24
TN_MEMPLL
-
Test terminal
AF25
RDQ16_B
I/O
Two-way data bus with the SD-RAM
AF26
DGND
-
Ground terminal
AF27
RDQS3_B
O
Data strobe signal (negative) output to the SD-RAM
AF28
RDQS3_B_
O
Data strobe signal (positive) output to the SD-RAM
AG1,
AG2
NFD3, NFD0
I/O
Two-way data bus with the NAND fl ash
AG3
NFCLE
O
Command latch enable signal output to the NAND fl ash
AG4
NFWEN
O
Write enable signal output to the NAND fl ash
AG5
SFDI
O
LPF selection signal output terminal Not used
AG7,
AG8
RDQ16, RDQ19
I/O
Two-way data bus with the SD-RAM
AG9
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG10
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG11
RDQ29
I/O
Two-way data bus with the SD-RAM
AG13
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG14
RBA0
O
Bank address signal output to the SD-RAM
AG16
RCKE
O
Clock enable signal output to the SD-RAM
AG17
RDQ0
I/O
Two-way data bus with the SD-RAM
AG19
RDQ9
I/O
Two-way data bus with the SD-RAM
AG20
RDQS0
O
Data strobe signal (positive) output to the SD-RAM
AG21
RDQS1_
O
Data strobe signal (negative) output to the SD-RAM
AG22
RDQ7
I/O
Two-way data bus with the SD-RAM
AG24
RCLK0
O
Clock signal (positive) output to the SD-RAM
AG25
RDQ17_B
I/O
Two-way data bus with the SD-RAM
AG26
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AG27
RDQS2_B
O
Data strobe signal (negative) output to the SD-RAM
AG28
RDQS2_B_
O
Data strobe signal (positive) output to the SD-RAM
AH1
NFD1
I/O
Two-way data bus with the NAND fl ash
AH2
NFCEN
O
Chip enable signal output to the NAND fl ash
AH4
SFDO
O
Serial data output terminal Not used
AH5
SFCS
O
USB VBUS on/off control signal output terminal Not used
AH7,
AH8
RDQ17, RDQ18
I/O
Two-way data bus with the SD-RAM
AH9
RDQS2_
O
Data strobe signal (negative) output to the SD-RAM
AH10
RDQS3
O
Data strobe signal (positive) output to the SD-RAM
AH11
RDQ28
I/O
Two-way data bus with the SD-RAM
AH13
RCLK1_
O
Clock signal (negative) output to the SD-RAM
AH14
RA3
O
Address signal output to the SD-RAM
AH16,
AH17
RA8, RA10
O
Address signal output to the SD-RAM
AH19
RDQ8
I/O
Two-way data bus with the SD-RAM
AH20
RDQS0_
O
Data strobe signal (negative) output to the SD-RAM
AH21
RDQS1
O
Data strobe signal (positive) output to the SD-RAM
AH22
RDQ13
I/O
Two-way data bus with the SD-RAM
AH24
RCLK0_
O
Clock signal (negative) output to the SD-RAM
AH25 to
AH28
RDQ18_B, RDQ19_B,
RDQ26_B, RDQ27_B
I/O
Two-way data bus with the SD-RAM
HBD-E280/T28
74
MB-141 BOARD IC6201 R5F3650KBDFA (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
BD_SDI
O
Serial data output to the BD decoder
2
BD_SCLK
I
Serial data transfer clock signal input from the BD decoder
3
NO USE
I
Not used
4
SIRCS_IN
I
SIRCS signal input from the remote control receiver
5
FL_DOUT
O
Serial data output to the fl uorescent indicator tube driver
6
S-AIR_GPIO2
I
Interrupt signal input terminal Not used
7
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube driver
8
BYTE
I
External data bus width selection signal input terminal
9
CNVss
I
Processor mode selection signal input terminal
10
ADC_PDN
O
Power down signal output terminal Not used
11
NO USE
O
Not used
12
RESET
I
System reset signal input from the reset signal generator and reset switch “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
13
Xout
O
System clock output terminal (8 MHz)
14
Vss
-
Ground terminal
15
Xin
I
System clock input terminal (8 MHz)
16
Vcc
-
Power supply terminal (+3.3V)
17
CEC (TX/RX)
I/O
CEC serial data input/output with the HDMI connector
18
TS_INT
I
Touch sensor detection signal input terminal Not used
19
KEY_INT
I
Key wake-up signal input terminal
20
AC_CUT
I
AC cut detection signal input terminal “L”: AC cut
21
BD_IF_START
O
Ready signal output to the BD decoder “H”: ready
22
LED_PWM3
O
LED drive signal output terminal Not used
23
TS_RST
O
Touch sensor reset signal output terminal Not used
24
PCONT_TS
O
Power supply on/off control signal output terminal Not used
25
BD_IF_REQ
I
Request signal input from the BD decoder
26
LED_PWM2
O
LED drive signal output terminal Not used
27
PCONT_FL
O
Power supply on/off control signal output terminal for fl uorescent indicator tube driver
“H”: power on
“H”: power on
28
LED_PWM1
O
LED drive signal output terminal Not used
29
S-AIR_SCL
I/O
Two-way I2C clock bus terminal Not used
30
S-AIR_SDA
I/O
Two-way I2C data bus terminal Not used
31
TXD1
O
Not used
32
RXD1
I
Not used
33
CLK1
O
Not used
34
RTS1
O
Not used
35
DAMP_SCDT
O
Serial data output to the stream processor
36
DC_DET
I
Speaker DC detection signal input terminal “L”: speaker DC is detected
37
DAMP_SHIFT
O
Serial data transfer clock signal output to the stream processor
38
PCONT_CORE
O
Power supply on/off control signal output terminal “H”: power on
39
PCONT2
O
Power supply control signal output terminal Not used
40
PCONT3
O
Power supply on/off control signal output terminal “H”: power on
41
PCONT4
O
Power supply control signal output terminal Not used
42
HDMI_PCONT
O
Power supply control signal output terminal Not used
43
ATA_PCONT1
O
Power supply on/off control signal output terminal “H”: power on
44
FAN_ON
O
Power supply on/off control signal output terminal for fan motor “H”: power on
45
FAN_CONT
O
Fan motor on/off control signal output terminal “H”: motor on
46
CE
I
Chip enable signal input terminal Not used
47
ST_SDA
I/O
Two-way data bus with the FM receiver
48
ST_SCL
O
Serial data transfer clock signal output to the FM receiver
49
NO USE
O
Not used
50
DRIVER_RST (EN)
O
Reset signal output to the power amplifi er “L”: reset
51, 52
OVERFLOW1,
OVERFLOW2
I
Overfl ow detection signal input from the stream processor
53
DAMP_INIT
O
Reset signal output to the stream processor “L”: reset
54
DAMP_SOFT_MUTE
O
Soft muting on/off control signal output to stream processor “L”: muting on
55
DAMP_LATCH1
O
Serial data latch pulse signal output to the stream processor
56
DAMP_LATCH2
O
Serial data latch pulse signal output to the stream processor
57
DAMP_LATCH3
O
Serial data latch pulse signal output to the stream processor
HBD-E280/T28
75
Pin No.
Pin Name
I/O
Description
58
KARAOKE_MODE
I
Karaoke mode information input terminal Not used
59
MIC_CLK
O
Clock signal output terminal Not used
60
MIC_DATA
O
Serial data output terminal Not used
61
MIC_DET_OUT
O
Microphone detection signal output terminal Not used
62
Vcc
-
Power supply terminal (+3.3V)
63
S-AIR_RST
O
Reset signal output terminal Not used
64
Vss
-
Ground terminal
65
PLUG_DET
I
Calibration microphone plug insert detection signal input terminal Not used
66
S-AIR_RF_FB
I
RF feedback signal output terminal Not used
67
DRIVER_SD
I
Shut down signal input from the power amplifi er “L”: shut down
68
ACAL_OUT
I
Auto calibration output detection signal input terminal Not used
69
FE_RST_IF
O
Reset signal output terminal Not used
70
FL_CS
O
Chip select signal output to the fl uorescent indicator tube driver
71
ASEL_0
O
Audio selection signal output terminal “L”: external audio input , “H”: FM
72
ASEL_1
O
Audio selection signal output terminal Not used
73, 74
NO USE
O
Not used
75
ST_RDS_INT
I
RDS interrupt signal input from the FM receiver
76
NO USE
O
Not used
77
TS_SDA
I/O
Two-way data bus Not used
78
TS_SCL
I/O
Two-way clock bus Not used
79
ATA_PCONT2
O
Power supply control signal output terminal Not used
80
NO USE
O
Not used
81
SRS_INT
O
Reset signal output terminal Not used
82
PCONT1
O
Power supply on/off control signal output terminal “H”: power on
83
BD_RESET
O
Reset signal output to the BD decoder, NAND fl ash and EEPROM “L”: reset
84
JIG_MODE1
I
Jig mode selection signal input from the BD decoder
85
OPWRSB
I
Power control signal input from the BD decoder
86
FE_EJECT
O
Eject/stop key input detection signal output to the BD decoder
87
UPG_STATUS
I
UPG status signal input from the BD decoder
88
BD_CS
O
Chip select signal output to the BD decoder
89
ACAL_LV
I
Microphone input level detection signal input terminal Not used
90
S-AIR_DET
I
Wireless transceiver detection signal output terminal Not used
91
BD_TEMP
I
Temperature detection signal input terminal
92
DESTINATION
I
Destination setting terminal
93
MODEL
I
Model setting terminal Fixed at “L” in this unit
94, 95
KEY2, KEY1
I
Key input terminal for front panel keys
96
Vss
-
Ground terminal
97
KEY0
I
Power supply key input terminal
98
Vref
I
Reference voltage (+3.3V) input terminal
99
Vcc
-
Power supply terminal (+3.3V)
100
BD_SDO
I
Serial data input from the BD decoder
76
HBD-E280/T28
SECTION 6
EXPLODED VIEWS
1
4-264-108-01 PANEL,
LOADING
2
X-2560-834-1 FRONT PANEL ASSY (E280: PX)
2
X-2560-923-1 FRONT PANEL ASSY (E280: US)
2
X-2560-924-1 FRONT
PANEL
ASSY
(E280: AEP, IT, RU, UK, AUS, MX)
2
X-2560-927-1 FRONT PANEL ASSY (T28: MX)
2
X-2580-970-1 FRONT PANEL ASSY (E280: CND)
2
X-2580-971-1 FRONT PANEL ASSY (T28: CND)
3
3-077-331-21 +BV3
(3-CR)
4
4-264-111-01 CASE
(E0)
5
4-162-271-01 SCREW,
TAPPING
Ref. No.
Part No.
Description
Remark
Ref. No.
Part No.
Description
Remark
Note:
• -XX and -X mean standardized parts, so
• -XX and -X mean standardized parts, so
they may have some difference from the
original one.
original one.
• Items marked “*” are not stocked since
they are seldom required for routine ser-
vice. Some delay should be anticipated
when ordering these items.
vice. Some delay should be anticipated
when ordering these items.
• The mechanical parts with no reference
number in the exploded views are not sup-
plied.
plied.
• Color Indication of Appearance Parts Ex-
ample:
KNOB, BALANCE (WHITE) . . . (RED)
Parts Color Cabinet’s Color
• Abbreviation
AUS :
AUS :
Australian
model
CND : Canadian model
IT
IT
: Italian model
MX
: Mexican model
RU
: Russian model
6-1. CASE, FRONT PANEL SECTION
The components identifi ed by mark 0
or dotted line with mark 0 are critical for
safety.
Replace only with part number specifi ed.
or dotted line with mark 0 are critical for
safety.
Replace only with part number specifi ed.
Les composants identifi és par une marque
0 sont critiques pour la sécurité.
Ne les remplacer que par une pièce por-
tant le numéro spécifi é.
0 sont critiques pour la sécurité.
Ne les remplacer que par une pièce por-
tant le numéro spécifi é.
The components identifi ed by mark 9 con-
tain confi dential information.
Strictly follow the instructions whenever the
components are repaired and/or replaced.
tain confi dential information.
Strictly follow the instructions whenever the
components are repaired and/or replaced.
Les composants identifi és par la marque
9 contiennent des informations confi den-
tielles.
Suivre scrupuleusement les instructions
chaque fois qu’un composant est remplacé
et / ou réparé.
9 contiennent des informations confi den-
tielles.
Suivre scrupuleusement les instructions
chaque fois qu’un composant est remplacé
et / ou réparé.
1
2
4
5
5
3
3
power block section
Ver. 1.2
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