Sony BDV-E280 / BDV-T28 / HBD-E280 / HBD-T28 Service Manual ▷ View online
HBD-E280/T28
69
Pin No.
Pin Name
I/O
Description
N10
DVCC10_K
-
Power supply terminal (+1.1V)
N11 to
N17
DGND
-
Ground terminal
N18
DVCC10_K
-
Power supply terminal (+1.1V)
N19
DGND
-
Ground terminal
N21
DGND
-
Ground terminal
N23, N24
RDQ14_B, RDQ15_B
I/O
Two-way data bus with the SD-RAM
N25
DGND
-
Ground terminal
N26 to
N28
RDQ12_B, RDQ7_B,
RDQ6_B
I/O
Two-way data bus with the SD-RAM
P1
FEFMO3
O
Stepping motor drive signal output to the motor driver
P2, P3
FEMPXOUT1,
FEMPXOUT3
O
Monitoring signal output terminal
P4
FEGAINSW2
O
Enable signal output to the motor driver
P5
FECFREQ
I/O
Two-way data bus with the BD drive
P6
FE_GAINSW3
O
Gain control signal output to the coil/motor driver
P8
DVCC33_IO
-
Power supply terminal (+3.3V)
P10
DGND
-
Ground terminal
P11
DVCC10_K
-
Power supply terminal (+1.1V)
P12 to
P18
DGND
-
Ground terminal
P19
DVCC10_K
-
Power supply terminal (+1.1V)
P21
DVCC15_IO_1
-
Power supply terminal (+1.5V)
P23, P24
RDQ8_B, RDQ13_B
I/O
Two-way data bus with the SD-RAM
P25
RDQM0_B
O
Data mask signal output to the SD-RAM
P26
DVCC15_IO_1
-
Power supply terminal (+1.5V)
P27
RDQS1_B
O
Data strobe signal (negative) output to the SD-RAM
P28
RDQS1_B_
O
Data strobe signal (positive) output to the SD-RAM
R3
FECMOD
O
Serial interface command enable signal output to the BD drive
R4
REIC_MUTE1
O
Motor drive muting control signal output to the coil/motor driver
R5
FEOSCEN
O
Serial data transfer clock signal output to the BD drive
R6
REIC_MUTE2
O
Motor drive muting control signal output to the coil/motor driver
R10
DVCC10_K
-
Power supply terminal (+1.1V)
R11 to
R17
DGND
-
Ground terminal
R18
DVCC10_K
-
Power supply terminal (+1.1V)
R19
DGND
-
Ground terminal
R21
DGND
-
Ground terminal
R23
RVREF_4
I
Reference voltage (+0.75V) input terminal for SD-RAM
R24
RDQM1_B
O
Data mask signal output to the SD-RAM
R25
DVCC15_IO_1
-
Power supply terminal (+1.5V)
R26
DGND
-
Ground terminal
R27
RDQS0_B
O
Data strobe signal (negative) output to the SD-RAM
R28
RDQS0_B_
O
Data strobe signal (positive) output to the SD-RAM
T1
FEGAINSW1
O
Mode B selection signal output to the BD drive
T2
FEGIO2
I
Slot loading detection switch input terminal Not used
T3
FEGIO4
-
Not used
T4
FEGIO8
I
Slot loading detection switch input terminal Not used
T5
FEGIO13
O
Transmit data output terminal
T6
FEGIO3
I
Eject/stop key input detection signal input from the system controller
T8
DVCC33_IO
-
Power supply terminal (+3.3V)
T10
DGND
-
Ground terminal
T11
DVCC10_K
-
Power supply terminal (+1.1V)
T12 to
T18
DGND
-
Ground terminal
T19
DVCC10_K
-
Power supply terminal (+1.1V)
T21
DVCC15_IO_1
-
Power supply terminal (+1.5V)
T23
RDQ11_B
I/O
Two-way data bus with the SD-RAM
T24
RBA1_B
O
Bank address signal output to the SD-RAM
T25 to
T28
RDQ0_B, RDQ1_B,
RDQ10_B, RDQ9_B
I/O
Two-way data bus with the SD-RAM
HBD-E280/T28
70
Pin No.
Pin Name
I/O
Description
U1
FEGIO5
O
Mode A selection signal output to the BD drive
U2
FEGIO6
O
Mode C selection signal output terminal Not used
U3
FEGIO10
I
Receive data input terminal
U4
FEEJECT_
I
Eject/stop key input detection signal input terminal Not used
U5
FEGIO11
O
Transmit data output terminal
U6
FEGIO12
O
Jig mode selection signal output terminal
U9
DGND
-
Ground terminal
U10
DVCC10_K
-
Power supply terminal (+1.1V)
U11 to
U17
DGND
-
Ground terminal
U18
DVCC10_K
-
Power supply terminal (+1.1V)
U19
DGND
-
Ground terminal
U21
DGND
-
Ground terminal
U23, U24
RA12_B, RA1_B
O
Address signal output to the SD-RAM
U25, U26
RDQ3_B, RDQ2_B
I/O
Two-way data bus with the SD-RAM
V3
FEGIO9
-
Not used
V4
FELIMIT_
I
Sledge inner limit detection signal input from the coil/motor driver
V5
FETRAYOUT
I
Disc tray in detection signal input from the BD drive
V6
REIC_TRAYIN#
I
Disc tray out detection signal input from the BD drive
V9
DVCC10_K
-
Power supply terminal (+1.1V)
V10
DGND
-
Ground terminal
V11
DVCC10_K
-
Power supply terminal (+1.1V)
V12
DGND
-
Ground terminal
V13
DVCC10_K
-
Power supply terminal (+1.1V)
V14
DGND
-
Ground terminal
V15
DVCC10_K
-
Power supply terminal (+1.1V)
V16
DGND
-
Ground terminal
V17
DVCC10_K
-
Power supply terminal (+1.1V)
V18
DGND
-
Ground terminal
V19
DVCC10_K
-
Power supply terminal (+1.1V)
V21
DVCC15_IO_1
-
Power supply terminal (+1.5V)
V23, V24
RA11_B, RA4_B
O
Address signal output to the SD-RAM
V25
DGND
-
Ground terminal
V26
DVCC15_IO_1
-
Power supply terminal (+1.5V)
V27
RACK_B
O
Clock enable signal output to the SD-RAM
V28
RA10_B
O
Address signal output to the SD-RAM
W1
STXP
O
Transmit data (positive) output terminal Not used
W2
STXN
O
Transmit data (negative) output terminal Not used
W3
GIO7
O
Laser diode control signal output to the BD drive
W4
FEPLAY_
I
Play/pause key input detection signal input terminal Not used
W5
REIC_FG
I
Motor hole sensor signal input from the coil/motor driver
W6
AVSS_12SATA1
-
Ground terminal
W9
DGND
-
Ground terminal
W10
DVCC10_K
-
Power supply terminal (+1.1V)
W11
DGND
-
Ground terminal
W12
DVCC10_K
-
Power supply terminal (+1.1V)
W13
DGND
-
Ground terminal
W14
DVCC10_K
-
Power supply terminal (+1.1V)
W15
DGND
-
Ground terminal
W16
DVCC10_K
-
Power supply terminal (+1.1V)
W17
DGND
-
Ground terminal
W18
DVCC10_K
-
Power supply terminal (+1.1V)
W19
DGND
-
Ground terminal
W21
DGND
-
Ground terminal
W24
RA6_B
O
Address signal output to the SD-RAM
W25
RBA2_B
O
Bank address signal output to the SD-RAM
W26 to
W28
RA9_B, RA7_B,
RA2_B
O
Address signal output to the SD-RAM
Y1
SRXN
I
Receive data (negative) input terminal Not used
Y2
SRXP
I
Receive data (positive) input terminal Not used
HBD-E280/T28
71
Pin No.
Pin Name
I/O
Description
Y3
AVDD12_SATA1
-
Power supply terminal (+1.2V)
Y4
SREXT
-
External reference resistor connection terminal Not used
Y5
AVDD33_SATA
-
Power supply terminal (+3.3V)
Y8
DVCC33_IO_2
-
Power supply terminal (+3.3V)
Y20
DVCC15_IO_1
-
Power supply terminal (+1.5V)
Y24, Y25
RA8_B, RA13_B
O
Address signal output to the SD-RAM
Y26
RRESET_B
O
Reset signal output to the SD-RAM “L”: reset
AA3,
AA4
AVDD33_USB_1P_1,
AVDD33_USB_2P_2
-
Power supply terminal (+3.3V)
AA5,
AA6
AVSS33_USB_2P_2,
AVSS33_USB_1P_1
-
Ground terminal
AA8
DVCC33_IO_2
-
Power supply terminal (+3.3V)
AA11
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA12
DGND
-
Ground terminal
AA13
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA14
DGND
-
Ground terminal
AA15
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA16
DGND
-
Ground terminal
AA17
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA18
DGND
-
Ground terminal
AA19
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA20,
AA21
RVREF_2, RVREF_3
I
Reference voltage (+0.75V) input terminal for SD-RAM
AA23,
AA24
RDQ22_B, RDQ20_B
I/O
Two-way data bus with the SD-RAM
AA25
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AA26
DGND
-
Ground terminal
AA27,
AA28
RA3_B, RA5_B
O
Address signal output to the SD-RAM
AB1
USB_1P_DM
I/O
Two-way USB serial data (–) bus with the USB connector (rear side)
AB2
USB_1P_DP
I/O
Two-way USB serial data (+) bus with the USB connector (rear side)
AB3
AVDD12_USB_1P_1
-
Power supply terminal (+1.2V)
AB5
AVSS12_USB_2P_1A
-
Ground terminal
AB6
AVSS12_USB_1P_1
-
Ground terminal
AB11
DGND
-
Ground terminal
AB12
RVREF_1
I
Reference voltage (+0.75V) input terminal for SD-RAM
AB23,
AB24
RDQ23_B, RDQ21_B
I/O
Two-way data bus with the SD-RAM
AB25
RCS_B
O
Chip select signal output to the SD-RAM
AB26
RBA0_B
O
Bank address signal output to the SD-RAM
AB27
RCLK1_B
O
Clock signal (positive) output to the SD-RAM
AB28
RCLK1_B_
O
Clock signal (negative) output to the SD-RAM
AC1
USB_2P_DM1
I/O
Two-way USB serial data (–) bus terminal Not used
AC2
USB_2P_DP1
I/O
Two-way USB serial data (+) bus terminal Not used
AC3
USB_1P_VRT
-
External reference resistor connection terminal
AC4
AVDD12_USB_2P_1A
-
Power supply terminal (+1.2V)
AC7
GPIO7
O
USB VBUS on/off control signal output terminal for USB connector “H”: VBUS on
AC9
EFPWRQ
-
Power supply terminal (+2.5V) Not used
AC12
RDQ12
I/O
Two-way data bus with the SD-RAM
AC13
RRAS_
O
Row address strobe signal output to the SD-RAM
AC14
RODT
O
On die termination enable signal output to the SD-RAM
AC15
RBA2
O
Bank address signal output to the SD-RAM
AC16
RRESET
O
Reset signal output to the SD-RAM “L”: reset
AC17,
AC18
RA6, RA12
O
Address signal output to the SD-RAM
AC20
RDQ10
I/O
Two-way data bus with the SD-RAM
AC22
RDQ4
I/O
Two-way data bus with the SD-RAM
AC23 to
AC25
RDQ31_B, RDQ30_B,
RDQ28_B
I/O
Two-way data bus with the SD-RAM
AC26
RCAS_B
O
Column address signal output to the SD-RAM
HBD-E280/T28
72
Pin No.
Pin Name
I/O
Description
AD1
USB_2P_DM0
I/O
Two-way USB serial data (–) bus with the USB connector (front side)
(E280: AEP, Italian, Russian, UK, Australian, Mexican/T28: Mexican models only)
(E280: AEP, Italian, Russian, UK, Australian, Mexican/T28: Mexican models only)
AD2
USB_2P_DP0
I/O
Two-way USB serial data (+) bus with the USB connector (front side)
(E280: AEP, Italian, Russian, UK, Australian, Mexican/T28: Mexican models only)
(E280: AEP, Italian, Russian, UK, Australian, Mexican/T28: Mexican models only)
AD3
USB_2P_VRT
-
External reference resistor connection terminal
AD4
NFREN
O
Read enable signal output to the NAND fl ash
AD5
NFCEN2
O
Chip enable signal output terminal Not used
AD6
GPIO4
O
Jig mode selection signal output terminal
AD7
TCK
I
Clock signal input terminal
AD8
TDI
I
Serial data input terminal
AD9,
AD10
RDQM3, RDQM2
O
Data mask signal output to the SD-RAM
AD12
RDQ23
I/O
Two-way data bus with the SD-RAM
AD13
RA0
O
Address signal output to the SD-RAM
AD14
RCAS_
O
Column address signal output to the SD-RAM
AD15 to
AD18
RA5, RA13,
RA11, RA4
O
Address signal output to the SD-RAM
AD19
RBA1
O
Bank address signal output to the SD-RAM
AD20
RDQ11
I/O
Two-way data bus with the SD-RAM
AD21
RDQM1
O
Data mask signal output to the SD-RAM
AD22
RDQ14
I/O
Two-way data bus with the SD-RAM
AD23
AVSS12_MEMPLL
-
Ground terminal
AD24,
AD25
RDQ29_B, RDQ24_B
I/O
Two-way data bus with the SD-RAM
AD26
RDQM2_B
O
Data mask signal output to the SD-RAM
AD27
RODT_B
O
On die termination enable signal output to the SD-RAM
AD28
RRAS_B
O
Row address signal output to the SD-RAM
AE1,
AE2
NFD7, NFD6
I/O
Two-way data bus with the NAND fl ash
AE3
NFRBN
O
Ready/busy selection signal output to the NAND fl ash “L”: busy, “H”: ready
AE4
NFRBN2
O
Ready/busy selection signal output terminal Not used
AE5
GPIO6
O
UPG status signal output to the system controller
AE6
GPIO5
O
Jig mode selection signal output to the system controller
AE7
TMS
I
Mode selection signal input terminal
AE8,
AE9
RDQ24, RDQ26
I/O
Two-way data bus with the SD-RAM
AE10
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AE11,
AE12
RDQ31, RDQ21
I/O
Two-way data bus with the SD-RAM
AE13
RWE_
O
Write enable signal output to the SD-RAM
AE14
DGND
-
Ground terminal
AE15
RCS_
O
Chip select signal output to the SD-RAM
AE16
RA7
O
Address signal output to the SD-RAM
AE17
DVCC15_IO_1
-
Power supply terminal (+1.5V)
AE18
RDQ2
I/O
Two-way data bus with the SD-RAM
AE19
RA1
O
Address signal output to the SD-RAM
AE20
DGND
-
Ground terminal
AE21
RDQM0
O
Data mask signal output to the SD-RAM
AE22
RDQ12
I/O
Two-way data bus with the SD-RAM
AE23
AVDD12_MEMPLL
-
Power supply terminal (+1.2V)
AE24
TP_MEMPLL
-
Test terminal
AE25
RDQ25_B
I/O
Two-way data bus with the SD-RAM
AE26
RDQM3_B
O
Data mask signal output to the SD-RAM
AE27
RA0_B
O
Address signal output to the SD-RAM
AE28
RWE_B
O
Write enable signal output to the SD-RAM
AF1 to
AF3
NFD5, NFD4, NFD2
I/O
Two-way data bus with the NAND fl ash
AF4
NFALE
O
Address latch enable signal output to the NAND fl ash
AF5
SFCK
O
Serial data transfer clock signal output terminal Not used
AF6
TDO
O
Serial data output terminal
AF7
TRST_
I
Reset signal input terminal “L”: reset
Ver. 1.2
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