Sony AVD-K800P / HT-C800DP Service Manual ▷ View online
61
AVD-K800P
4-26. IC Pin Function Description
• IC207 ZIVA5X-C1F (DVD SYSTEM PROCESSOR)(DMB03 BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I
I/O
I/O
I/O
I/O
—
—
—
—
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
Pin Name
VDDP
HA1
HAD15
HAD14
HAD13
HAD12
HAD11
HAD10
HAD9
HAD8
HAD7
VDDP
GNDP
HAD6
HAD5
HAD4
HAD3
HAD2
HAD1
VDDP
GNDP
HAD0
HDTACK
HIRQ0
WEH.UDS
WEL.LDS
HREAD
GPIO0
GND
VDD
GND25
VDD25
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
GND25
VDD25
MA10
MA11
BA1
BA0
MCS0
MCS1
Description
Power supply terminal (+3.3V) (I/O signal)
Address bus
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Data bus (address signal multiplexed)
Acknowledge signal input/output for host data transfer (not used)
Interrupt signal input for Medusa (not used)
Host upper data strobe signal output
Host lower data strobe signal output (not used)
Read/write strobe signal output
Jig detection port (pull-up)
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM address bus
SDRAM address bus
SDRAM bank select 1 signal output
SDRAM bank select 0 signal output
SDRAM chip select 0 signal output
Not used
62
AVD-K800P
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
O
—
—
O
I/O
I/O
I/O
I/O
—
O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
—
O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
—
I/O
I/O
Pin Name
MRAS
MCAS
MWE
GND25
VDD25
MCLK
MD0
MD1
MD2
MD3
GND25
MDQM0
VDD25
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
GND25
MDQM1
VDD25
MD12
MD13
MD14
MD15
GND
VDD
MD16
MD17
MD18
MD19
GND25
MDQM2
VDD25
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
GND25
MDQM3
VDD25
MD28
MD29
Description
SDRAM row address strobe signal output
SDRAM column address strobe signal output
SDRAM write enable signal output (“H” : read, “L” : write)
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM Clock output
SDRAM data
SDRAM data
SDRAM data
SDRAM data
Ground terminal (SDRAM I/O signal)
Byte read /write mask signal 0 output
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
Ground terminal (SDRAM I/O signal)
Byte read /write mask signal 1 output
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM data
SDRAM data
SDRAM data
SDRAM data
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
SDRAM data
SDRAM data
SDRAM data
SDRAM data
Ground terminal (SDRAM I/O signal)
Byte read /write mask signal 2 output
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
SDRAM data
Ground terminal (SDRAM I/O signal)
Byte read /write mask signal 3 output
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM data
SDRAM data
63
AVD-K800P
Pin No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
I/O
I/O
I/O
—
—
I/O
I/O
O
O
O
O
—
—
O
O
O
I
—
—
O
—
—
O
—
—
O
—
—
O
—
—
O
—
—
—
I
—
—
O
I
—
—
—
—
—
—
—
O
O
O
O
Pin Name
MD30
MD31
GND25
VDD25
VCLK
XCK_I/O_SEL
VS
I/P SW
CDSEL
MREQ
VDDP
GNDP
MDI
MC
ML
HIRQ2_
VDAC_4B
VDAC_VDD4
VDAC_4
VDAC_3B
VDAC_VDD3
VDAC_3
VDAC_2B
VDAC_VDD2
VDAC_2
VDAC_1B
VDAC_VDD1
VDAC_1
VDAC_0B
VDAC_VDD0
VDAC_0
VDAC_DVSS
VDAC_DVDD
VDAC_REFVDD
VDAC_REF
VDAC_REFVSS
XVSS
XOUT
XIN
XVDD
AVSS2
AVDD2
AVDD1
AVSS1
VDD
GND
XCK
LRCK
BCK
DATA0(DM)
Description
SDRAM data
SDRAM data
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
System clock (not used)
5.1ch/downmix switch signal output
S1 signal output (not used)
Progressive/interlace switch signal output (not used)
CD-DA selection signal output (not used)
Audio muting request signal output
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Serial data output to the D/A converter (IC302)
Serial data clock output to the D/A converter (IC302)
Latch enable signal output to the D/A converter (IC302)
Busy signal input from the EEPROM (IC204)
Video DAC bias bit 4 (connected to the ground)
Power supply terminal (+3.3V) (Video DAC 4)
VDAC output 4
Video DAC bias bit 3 (connected to the ground)
Power supply terminal (+3.3V) (Video DAC 3)
VDAC output 3
Video DAC bias bit 2 (connected to the ground)
Power supply terminal (+3.3V) (Video DAC 2)
VDAC output 2
Video DAC bias bit 1 (connected to the ground)
Power supply terminal (+3.3V) (Video DAC 1)
VDAC output 1 (not used)
Video DAC bias bit 0 (connected to the ground)
Power supply terminal (+3.3V) (Video DAC 0)
VDAC output 0
Ground terminal (Video DAC digital system)
Power supply terminal (+3.3V) (Video DAC digital system)
Power supply terminal (Video DAC reference)
Reference voltage input terminal(for Video DAC)
Ground terminal (Video DAC reference)
Ground terminal (crystal oscillator)
Crystal oscillation signal output (not used)
Crystal oscillation signal input
Power supply terminal (crystal oscillator)
Ground terminal (analog PLL)
Power supply terminal (+3.3V) (analog PLL)
Power supply terminal (+3.3V) (analog PLL)
Ground terminal (analog PLL)
Power supply terminal (+1.8V) (inside core)
Ground terminal (inside core)
Audio system clock output
LRCK signal output for audio
BCK signal output for audio
Audio data(Down Mix signal) output
64
AVD-K800P
Pin No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
I/O
O
—
—
O
O
O
I
I
I
I/O
I/O
O
I
O
O
—
—
I
I
I
I
—
—
I
I
I
I
O
I
—
—
I
I
I
I
I
O
I
—
O
O
O
O
I/O
O
—
I
O
I
I
Pin Name
DATA1(FLR)
VDDP
GNDP
DATA2(SLR)
DATA3(CSW)
IEC958
DAI_DATA
DAI_BCK
DAI_LRCK
I2C_CL
I2C_DA
CS(ZIVA_E2P)
RXD1
TXD1
WRITE_CTRL(ZIVA_E2P)
GNDP
VDDP
SDDATA7
SDDATA6
SDDATA5
SDDATA4
GND
VDD
SDDATA3
SDDATA2
SDDATA1
SDDATA0
SDREQ
SDEN
GNDP
VDDP
SDERROR
SDCLK
HIRQ1
DRVCLK
DRVTX
DRVRX
DRVRDY
VNW
ALE
RST_SPC
INT/EXT
HCS2
HCS1
HCS0
VDDP
TRST
TDO
TDI
TMS
Description
Audio data(Front L/R signal) output
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Audio data(Rear L/R signal) output
Audio data(Center/Subwoofer signal) output
S/PDIF signal (not used)
Data input from ADC (not used)
BCK signal input from ADC (not used)
LRCK signal input from ADC (not used)
I2C clock bus
I2C data bus
Chip select signal output to the EEPROM (IC204)
Serial data input for check jig
Serial data output for check jig
Write control signal output to the EEPROM (IC204)
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data7 input
SDBus data6 input
SDBus data5 input
SDBus data4 input
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
SDBus data3 input
SDBus data2 input
SDBus data1 input
SDBus data0 input
SDBus data request signal output
SDBus data enable signal input
Ground terminal (I/O signal)
Power supply terminal (+3.3V) (I/O signal)
SDBus data error signal input
SDBus data clock input
Interrupt signal input from the mechanism controller (IC901)
Serial data clock input from the mechanism controller (IC901)
Serial data input from the mechanism controller (IC901) and the EEPROM (IC204)
Serial data output to the mechanism controller (IC901) and the EEPROM (IC204)
Ready signal input from the mechanism controller (IC901)
Power supply for 5V tolerance voltage input
Latch enable signal output for address data demux
Reset signal output to the mechanism controller (IC901)
Input selection signal output for SDBus or ADC
Chip select signal output for Medusa (not used)
Not used
Chip select signal output to the external ROM (IC206)
Power supply terminal (+3.3V) (I/O signal)
Reset signal input
Data output
Data input
TMS signal input
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