Sharp LC-60LE651K Handy Guide ▷ View online
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Major IC Information…cont
October 2013
IC9552: USB 2.0 Hi-Speed Hub Controller
Part number: USB2514B-AEZG (SMSC)
Sharp code: VHI2514BAEZ-1Q
Sharp code: VHI2514BAEZ-1Q
http://www.smsc.com/Downloads/SMSC/Downloads_Public/Data_Sheets/251xb.pdf
The SMSC USB251x hub is a family of low-power, OEM configurable, MTT (multi transaction translator) 1 hub
controller IC products for embedded USB solutions. The “x” in the part number indicates the number of
downstream ports available. The SMSC hub supports low-speed, fullspeed, and hi-speed (if operating as a hi-speed
hub) downstream devices on all of the enabled downstream ports.
controller IC products for embedded USB solutions. The “x” in the part number indicates the number of
downstream ports available. The SMSC hub supports low-speed, fullspeed, and hi-speed (if operating as a hi-speed
hub) downstream devices on all of the enabled downstream ports.
Features
Full power management with individual or ganged power control of each
downstream port.
Fully integrated USB termination and pull-up/pull-down resistors.
Supports a single external 3.3 V supply source; internal regulators
provide 1.2 V or 1.8 V internal core voltage.
On-chip driver for 24 MHz crystal resonator or external 24/48 MHz clock.
Customizable vendor ID, product ID, and device ID.
ESD protection up to 4 kilovolts on all USB pins.
Supports self- or bus-powered operation.
USB251xB2 and USB251xBi products support the USB Battery
Charging specification.
Package: 36-pin QFN (6x6 mm).
Full power management with individual or ganged power control of each
downstream port.
Fully integrated USB termination and pull-up/pull-down resistors.
Supports a single external 3.3 V supply source; internal regulators
provide 1.2 V or 1.8 V internal core voltage.
On-chip driver for 24 MHz crystal resonator or external 24/48 MHz clock.
Customizable vendor ID, product ID, and device ID.
ESD protection up to 4 kilovolts on all USB pins.
Supports self- or bus-powered operation.
USB251xB2 and USB251xBi products support the USB Battery
Charging specification.
Package: 36-pin QFN (6x6 mm).
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Major IC Information…cont
October 2013
IC 3501, IC3502 & IC 3503: 2Gb 16Bits DDR3-1600 SDRAM
Part number: MT41J128M16JT-125:K (MICRON)
Sharp code: RH-IXD538WJZZQ
Sharp code: RH-IXD538WJZZQ
http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/2Gb_DDR3_SDRAM.pdf
DDR3 SDRAM uses double data rate architecture to achieve high-speed operation. The double data rate architecture is
an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O
pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the
DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3
SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of
CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on
the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE
command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with
the READ or WRITE commands are used to select the bank and the starting column location for the burst access.
an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O
pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the
DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3
SDRAM and edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is
referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of
CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on
the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE
command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with
the READ or WRITE commands are used to select the bank and the starting column location for the burst access.
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October 2013
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent
operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a powersaving, power-down mode.
Features:
VDD = VDDQ = 1.5V ±0.075V. 1.5V centre terminated push/pull I/O.
Differential bidirectional data strobe with 8n-bit prefetch architecture.
Differential clock inputs (CK, CK#).
8 internal banks.
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals.
Programmable CAS READ latency (CL). Posted
CAS additive latency (AL).
Programmable CAS WRITE latency (CWL) based on tCK.
Fixed burst length (BL) of 8 and burst chop
(BC) of 4 (via the mode register set [MRS]).
Self refresh temperature (SRT).
Multipurpose register with Output driver calibration.
timed row precharge that is initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent
operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a powersaving, power-down mode.
Features:
VDD = VDDQ = 1.5V ±0.075V. 1.5V centre terminated push/pull I/O.
Differential bidirectional data strobe with 8n-bit prefetch architecture.
Differential clock inputs (CK, CK#).
8 internal banks.
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals.
Programmable CAS READ latency (CL). Posted
CAS additive latency (AL).
Programmable CAS WRITE latency (CWL) based on tCK.
Fixed burst length (BL) of 8 and burst chop
(BC) of 4 (via the mode register set [MRS]).
Self refresh temperature (SRT).
Multipurpose register with Output driver calibration.
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Major IC Information…cont
October 2013
IC9551: Adjustable Current Limited Load Switch with Fault Flag (USB1).
Part number: AAT4614IGU-2-T1 (SKYWORKS INC.)
Sharp code: RH-IXD309WJZZY
Sharp code: RH-IXD309WJZZY
http://www.skyworksinc.com/uploads/documents/201939A.pdf
The AAT4614 Smart Switch is a current limited P-channel MOSFET power switch designed for high side load
switching applications. This switch operates with inputs ranging from 2.4V to 5.5V, making it ideal for both 3V and
5V systems. An integrated current-limiting circuit protects the input supply against large currents which may cause
the supply to fall out of regulation. Reverse current blocking is provided to protect the load switch from reverse
current potentials while the device is shutdown.
The AAT4614 is also protected from thermal overload which is limited by power dissipation and junction
temperatures. Current limit threshold is programmed with a resistor from SET to ground and may be adjusted for
levels up to 1.4A. The ultra-fast current limit response to a sudden short circuit is a mere 1μs which reduces the
requirements of local supply bypassing. An open drain FAULT flag signals an over-current or over-temperature
condition after a 4ms blanking time to prevent false reporting. Quiescent current is a low 10μA and the supply
current decreases to less than 1μA in shutdown mode.
The AAT4614 is offered in the 8-pin SC70JW, SOT23-6 and SOT23-5 packages, and is specified for operation over
the -40°C to +85°C ambient temperature range.
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