DOWNLOAD Sharp LC-46LE631E (serv.man2) Service Manual ↓ Size: 10.49 MB | Pages: 127 in PDF or view online for FREE

19100_058_110217.eps

110217

91

87

OUT

0

1

2

3

CTRL

H

D

M

I

HD

M

I

H

D

M

I

SPDIF

Output

VGA

HDMI

3

D

DDR2

DDR2

DDR2

DDR2

FLASH

PNX85500

M1

27x27

1.00mm

D

D

R

ETH

I²S

SPDIF

ANA
AUD

ANA

VID

STDBY

GPIO

HDMI

CA

TS-IN

LVDS-OUT

USB

Cl
as
s

-D

DC/DC

Ambilight

CPLD

C

Pr

oc

e

ss

S

u

pport

W

ire

He

a

d

Ph

o

n

e

L/R

1F24

SVC

SCART1/YPbPr

SD-SLOT

LONG

PCM

C

IA

PNX85500

M1

27x27

1.00mm

D

D

R

ETH

I²S

SPDIF

ANA
AUD

ANA

VID

STDBY

GPIO

HDMI

CA

TS-IN

LVDS-OUT

USB

Heatsink

DVB-S DC/DC

1M59

USB2.0

DVB-S DC/DC

T

DVB-S2

Hybrid

Tuner

uner

CD

7E01

1M95

1M99

1

M71

1E32

17

3

5

1D

38

1M20

1G50

1G

5

1

1M21

F-t

y

p

e

1

3

.65m

m

Y

L

R

Pb

Pr

Consult the Parts Listing at the end of this document for the 
order codes of the boards

The on-board DC/DC converters deliver the following voltages 
(depending on set execution):
•

+3V3-STANDBY, permanent voltage for the Stand-by 
controller, LED/IR receiver and controls; connector 1M95 
pin 1

•

+12V, input from the power supply for TV550 common 
(active mode); connector 1M95 pins 6, 7 and 8

•

+24V, input from the power supply for DVB-S2 (in active 
mode); connector 1M09 pins 1 and 2

•

+1V1, core voltage supply for PNX855xx; has to be started 
up first and switched "off" last (diagram B03B)

•

+1V2, supply voltage for analogue blocks inside PNX855xx

•

+1V8, supply voltage for DDR2 (diagram B03B)

•

+2V5, supply voltage for analogue blocks inside PNX855xx 
(see diagram B03E)

•

+3V3, general supply voltage (diagram B03E)

•

+5V, supply voltage for USB and CAM (diagram B03E)

•

+5V-TUN, supply voltage for tuner (diagram B03E)

•

+V-LNB, input voltage for LNB supply IC (item no. 7T50)

•

+5V-DVBS, input intermediate supply voltage for DVB-S2 
(diagram B08A)

•

+3V3-DVBS, clean voltage for silicon tuner and DVB-S2 
channel decoder

•

+2V5-DVBS, clean voltage for DVB-S2 channel decoder

•

+1V-DVBS, core voltage for DVB-S2 channel decoder.

A +12 V under-voltage detector (see diagram B03C) enables 
the 12V to 3.3V and 12V to 5V DC/DC converters via the 
ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter 
via the ENABLE-1V8 line. DETECT2 is the signal going to the 
Stand-by microcontroller and ENABLE-3V3n is the signal 
coming from the Stand-by microcontroller.

Diagram B03D contains the following linear stabilisers:
•

+2V5 stabiliser, built around item no. 7UCO

•

+5V-TUN stabiliser, built around items no. 7UA6 and 7UA7

•

+1V2 stabiliser, built around items no. 7UA3 and 7UA4.

Diagram B08A contains the DVB-S2-related DC/DC 
converters and -stabilisers:
•

a +24V under-voltage detection circuitry is built around 
item no. 7T04

•

the switching frequency of the 24 to 14...20V switched 
mode converter is 350 kHz (item no. 7T03 and +V-LNB 
lines)

•

the output signal on the +V-LNB line goes to the LNBH23Q 
(item no. 7T50)

•

the LNBH23Q (item no. 7T50) sends a feedback signal via 
the V0-CNTRL line

1

N

Anode 1+

+3V3stdby

2

L

n.c.

Standby

3

-

Cathode 1-

GND1

4

-

n.c.

GND1

5

-

Anode 2+

+12V

6

-

n.c.

+12V

7

-

Cathode 2-

+Vsnd (+24V)

8

-

n.c.

GND_SND

9

-

Anode 3+

BL-ON-OFF

10

-

n.c.

BL-DIM1 (Vsync)

11

-

Cathode 3-

BL-I-CTRL

12

-

n.c.

POK

13

-

Anode 4+

+24V (AL2_DVBS)

14

-

n.c.

GND1

15

-

Cathode 4-

-

1

N

Anode 1+

+3V3stdby

2

L

n.c.

Standby

3

-

Cathode 1-

GND1

4

-

n.c.

GND1

5

-

Anode 2+

+12V

6

-

n.c.

+12V

7

-

Cathode 2-

+Vsnd (+24V)

8

-

n.c.

GND_SND

9

-

Anode 3+

BL-ON-OFF

10

-

n.c.

BL-DIM1 (Vsync)

11

-

Cathode 3-

BL-I-CTRL

12

-

n.c.

POK

13

-

Anode 4+

+24V (AL2_DVBS)

14

-

n.c.

GND1

15

-

Cathode 4-

-

All power supplies are a black box for Service. When defective, 
a new board must be ordered and the defective one must be 
returned, unless the main fuse of the board is broken. Always 
replace a defective fuse with one with the correct 
specifications! This part is available in the regular market.

1

N

A2

+3V3SB

2

L

n.c.

Standby

3

-

pin 5

GND1

4

-

n.c.

GND1

5

-

pin 3

+12V3

6

-

n.c.

+12V3

7

-

OCD

+Vsnd

8

-

n.c.

GND1

9

-

A1

BL-ON-OFF

10

-

n.c.

BL-DIM1

11

-

pin 13

BL-I-CTRL

12

-

n.c.

POK

13

-

pin 11

+24V

14

-

n.c.

GND1

15

-

GND1

-

In this manual, no detailed information is available because of 
design protection issues.

•

the switching frequency of the +5V-DVBS to +1-DVBS 
switched mode converter is 900 kHz (item no. 7T00)

•

a delay line for the +2V5-DVBS and +1V-DVBS lines is 
created with item no. 3T03 (R=10k) and 2T06 (C=100n)

•

a 3.3V to 2.5V linear stabiliser is built around item no. 7T01

•

a 5V to 3.3V linear stabiliser is built around item no. 7T02.

Diagram B08B contains the DVB-S2 LNB supply:
•

the +V-LNB signal comes from item no. 7T03

•

the V0-CTRL signal goes to item no. 7T03

•

the LNB-RF1 goes to the LNB.

Figures gives a graphical representation of the DC/DC 
converters with its current consumptions:

The Front-End for the European/China region consist of the 
following key components:

•

Hybrid Tuner

•

Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter 
(8 MHz) (China)

•

Bandpass filter 

•

Amplifier

•

PNX855xx SoC TV processor with integrated DVB-T and 
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for this 
region.

The Front-End for the DVB-S(2) application consist of the 
following key components:

•

Satellite Tuner; I

2

C address 0xC6 (bridged via channel 

decoder)

•

Channel decoder; I

2

C address 0xD0

•

LNB switching regulator; I

2

C address 0x14

•

Amplifier

•

PNX855xx SoC TV processor with integrated DVB-T and 
DVB-C channel decoder and analogue demodulator.

Below find a block diagram of the front-end application for 
DVB-S(2) reception.

This application supports the following protocols:
•

Polarization selection via supply voltage (18V = horizontal, 
13V = vertical)

•

Band selection via “toneburst” (22 kHz): tone “on” = “high” 
band, tone “off” = “low” band

•

Satellite (LNB) selection via DiSEqC 1.0 protocol

•

Reception of DVB-S (supporting QPSK encoded signals) 
and DVB-S2 (supporting QPSK, 8PSK, 16APSK and 
32APSK encoded signals), introducing LDPC low-density 
parity check techniques.

In this platform, the Silicon Image Sil9x87 HDMI multiplexer is 
implemented. Refer to figure 

7-6 HDMI input configuration

 for 

the application.

18770_226_100127.eps

100426

+ 5V 5-T UN

196 m A

+ 5V

+ 5V 5-TUN

+ 5V -TUN

2179 m A

196 m A

+ 12V

+ 3V 3

+ 3V 3

+ 2V 5

2919 m A

2371 m A

450 m A

+ 1V 8

+ 1V 8

+ 1V 2

2450 m A

550 m A

+ 1V 1

5100 m A

+ 1V 1

dc -dc

+ 5V

dc -dc

+ 5V -TUN

s tabiliz er

+ 3V 3

dc -dc

+ 2V 5

s tabiliz er

+ 1V 8

dc -dc

+ 1V 2

s tabiliz er

18770_235_100127.eps

100219

18770_237_100127.eps

100219

The following multiplexers can be used:
•

Sil9187A (does not support “Instaport” technology for fast 
switching between input signals)

•

Sil9287B (supports “Instaport” technology for fast 
switching between input signals).

The hardware default I

2

C addresses are:

•

Sil9187A: 0xB0/0xB2 (random: software workaround)

•

Sil9287B: 0xB2 (fixed).

The Sil9x87 has the following specifications:
•

+5V detection mechanism

•

Stable clock detection mechanism

•

Integrated EDID

•

RT control

•

HPD control

•

Sync detection

•

TMDS output control

•

CEC control

•

EDID stored in Sil9x87, therefore there are no EDID pins 
on the SSB.

The PNX855xx is the main audio and video processor (or 
System-on-Chip) for this platform. It has the following features:

•

Multi-standard digital video decoder (MPEG-2, H.264, 
MPEG-4)

•

Integrated DVB-T/DVB-C channel decoder

•

Integrated CI+

•

Integrated motion accurate picture processing (MAPP2)

•

High definition ME/MC

•

2D LED backlight dimming option

•

Embedded HDMI HDCP keys

•

Extended colour gamut and colour booster

•

Integrated USB2.0 host controller

•

Improved MPEG artefact reduction compared with 
PNX8543

•

Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions, 
such as DVB-T channel decoding, MPEG-2/H.264 decode, 
analog video decode and HDMI reception, with advanced 
back-end video picture improvements. It also includes next 
generation Motion Accurate Picture Processing (MAPP2). The 
MAPP2 technology provides state-of-the-art motion artifact 
reduction with movie judder cancellation, motion sharpness 

and vivid colour management. High flat panel screen 
resolutions and refresh rates are supported with formats 
including 1366 × 768 @ 100Hz/120Hz and 1920 × 1080 @ 
100Hz/120Hz. The combination of Ethernet, CI+ and H.264 
supports new TV experiences with IPTV and VOD. On top of 
that, optional support is available for 2D dimming in 
combination with LED backlights for optimum contrast and 
power savings up to 50%.

For a functional diagram of the PNX855xx, refer 
to 

Figure 7-7

.

18770_243_100203.eps

100203