Sharp LC-40LU700E (serv.man10) Service Manual ▷ View online
LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 5
2.2. IC2002 (RH-iXC786WJQZQ)
2.2.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
LED_SLEEP
O
Sleep function ON/OFF
2
CEC_I2
I
Pull Up
3
AV_LINK_I
I
AV LINK Input
4
CEC_I
I
CEC Signal Input(1)
5
RC
I
Remote control signal input
6
BYTE
-
7
CNVSS
-
Debugger connection
8
XCIN
-
Sub-Clock connection
9
XCOUT
-
Sub-Clock connection
10
RESET
-
Reset
11
XOUT
-
System Clock
12
VSS
-
GND
13
XIN
-
System Clock
14
VCC1
-
Power supply(Bu3.3V)
15
(N.C.)
I
No function
16
P8_4
I
Pull down
17
ACCESS_G
O
No function
18
DET_SY(N.C.)
I
Error detection dor LCD Controller connection
19
ILL_LED
O
Illumination LED ON/OFF
20
AV_LINK_O
O
AV LINK output
21
MUTE_A_ALL
O
Sound Mute ON/OFF
22
CEC_O
O
CEC Signal Output
23
IRPASS
O
IR Pass Through
24
CEC_O2
O
No function
25
DET_COND
I
No function
26
W_PROT_M
O
EEPROM Write Protect
27
I2C_SCL
I2C
I2C Clock
28
I2C_SDA
I2C
I2C Data
29
TXD
-
Debugger connection
30
RXD
-
Debugger connection
31
SCLK
-
Debugger connection
32
BUSY
-
Debugger connection
33
DET_POW0
I
No function
34
DET_POW1(13V)
I
Power Error Detection(13V)
35
DET_POW2(PNL12V)
I
Power Error Detection(PNL12V)
36
DET_POW3(D3V3)
I
Power Error Detection(D3V3V)
37
DET_POW4
I
No function
38
DET_POW5
I
No function
39
EPM
-
Debugger connection
40
ERR_PNL
I
Lamp Error Detection
41
LNB_SHORT
I
Antenna short Detection
42
(N.C.)
No function
43
ANT_POW
O
Antenna Power Control
44
CE
-
Debugger connection
45
TXD_DBGP
O
Debugg Serial output
46
RXD_DBGP
I
Debugg Serial input
47
EXE_LED
O
LED for confirmation controller
48
N_SYSTEM_RST
I
Digital Reset SW
49
STB
O
Back light Reset
50
FRAME
O
LCD Controller control
51
ROMSEL0
O
Pull down
52
O_S_SET
O
Pull down
53
TEMP1
O
Pull down
54
TEMP2
O
Pull down
55
TEMP3
O
Pull down
56
L_R
O
Pull down
57
U_D
O
Pull down
58
COND_TEST
O
Pull down
59
SMPOW
O
13V supply on
60
VCC2
-
Power supply(Bu3.3V)
61
DPOW
O
DC-DC Enable
LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 6
62
VSS
-
GND
63
RS_ON
O
Power control for RS-232C Circuit
64
SY(N.C.)_DET
O
No function
65
HDMI_SCDT
I
No function
66
POW_SW
O
Power Key Detection
67
(N.C.)
No function
68
(N.C.)
No function
69
PL_POW
O
Panel Power ON
70
(N.C.)
71
CSEN2
I
No function
72
AC_DET
I
Detection for Power moment stop
73
VSY(N.C.)/DETECT
I
No function
74
CBOOT
O/D Main CPU boot change
75
TXD_CPU
O
MAIN CPU communication signal output
76
RXD_CPU
I
MAIN CPU communication signal input
77
PM_REQ
O
Communication Reset
78
SRESET
O/D Main CPU Reset
79
OPC
I
OPC input
80
QSTEMP
I
Thermistor Input
81
AFT/AGC
I
No function
82
KEY1
I
Key operation input
83
KEY2
I
Key operation input
84
KEY3
I
No function
85
(N.C.)
I
No function
86
MAIN_TEMP
I
No function
87
(N.C.)
I
No function
88
PNL_DET6
I
No function
89
PNL_DET5
I
No function
90
PNL_DET4
I
No function
91
PNL_DET3
I
No function
92
PNL_DET2
I
No function
93
PNL_DET1
I
No function
94
AVSS
-
GND
95
PNL_DET0
I
No function
96
VRFF
-
Analogue reference voltage
97
AVCC
-
Analogue power supply
98
LED_R
O
Red LED ON/OFF
99
LED_G
O
LED_Green ON/OFF
100
LED_OPC
O
OPC_LED On/OFF
Pin No.
Pin Name
I/O
Pin Function
LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 7
2.3. IC3501/3502 (RH-iXC790WJQZQ)
2.3.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
J8,K8
CK, CK#
I
Clock:
CK and CK# are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of crossing).
CK and CK# are differential clock inputs. All address and control input signals are sampled on the cross-
ing of the positive edge of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of crossing).
K2
CKE
I
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers.
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all bank idle), or Active
Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for
self refresh exit.
After VREF has become stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to
this input.
CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#,
ODT and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self
refresh.
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers.
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all bank idle), or Active
Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for
self refresh exit.
After VREF has become stable during the power on and initialization sequence, it must be maintained for
proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to
this input.
CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK#,
ODT and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self
refresh.
L8
CS#
I
Chip Select:
All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.
K9
ODT
I
On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM.
When enabled, ODT is only applied to each DQ, DQS, DQS#, RDQS, RDQS#, and DM signal for x4/x8
configuration.
For x16 configuration, ODT is applied to each DQ, UDQS/UDQS#. LDQS/LDQS#, UDM and LDM signal.
The ODT pin will be ignored if the Extended Mode Register Set (EMRS) is programmed to disable ODT.
ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM.
When enabled, ODT is only applied to each DQ, DQS, DQS#, RDQS, RDQS#, and DM signal for x4/x8
configuration.
For x16 configuration, ODT is applied to each DQ, UDQS/UDQS#. LDQS/LDQS#, UDM and LDM signal.
The ODT pin will be ignored if the Extended Mode Register Set (EMRS) is programmed to disable ODT.
K7,L7,K3
RAS#, CAS#, WE#
I
Command Inputs:
RAS#, CAS# and WE# (along with CS#) define the command being entered.
RAS#, CAS# and WE# (along with CS#) define the command being entered.
F3,B3
DM
(VDM) (UDM)
(VDM) (UDM)
I
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident
with that input data during a Write access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For x8 device, the function of DM or RDQS /RDQS# is enabled by EMRS command.
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident
with that input data during a Write access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For x8 device, the function of DM or RDQS /RDQS# is enabled by EMRS command.
L2,L3,L1
BA0, BA1, BA2
I
Bank Address Inputs:
BA0,BA1and BA2 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
BA0,BA1and BA2 define to which bank an Active, Read, Write or Precharge command is being applied.
Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
M8,M3,M
7,N2,N8,
N3,N7,P2
,P8,P3,M
2,P7,R2
A0 - A13
I
Address Inputs: Provide the row address for Active commands, and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective
bank.
A10 is sampled during a pre charge command to determine whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be Precharge, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
charge bit for Read/Write commands to select one location out of the memory array in the respective
bank.
A10 is sampled during a pre charge command to determine whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be Precharge, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
G8,G2,H
7,H3,H1,
7,H3,H1,
H9,F1,F9,
C8,C2,D7
C8,C2,D7
,D3,D1,D
9,B1,B9
DQ0 - DQ15
I/O
Data Input/Output: Bi-directional data bus.
B7,A8,
F7,E8
(DQS), (DQS#)
(LDQS0),(DQS0#)
or
(DQS3),(DQS3#)
(DQS2),(DQS2#)
(LDQS0),(DQS0#)
or
(DQS3),(DQS3#)
(DQS2),(DQS2#)
I/O
A2,E2,R3
,R7,R8
NC
-
No Connect: No internal electrical connection is present.
A1,E1,J9,
M9,R1
VDD
-
Power Supply: +1.8V
± 0.1V.
A9,C1,C3
,C7,C9,E
9,G1,G3,
9,G1,G3,
G7,G9
VDDQ
-
DQ Power Supply: +1.8V
± 0.1V.
A3,E3,J3,
N1,P9
VSS
-
Ground.
LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S
7 – 8
A7,B2,B8
,D2,D8,E
7,F2,F8,H
2,H8
VSSQ
-
Ground. DQ Ground.
J1
VDDL
-
DLL Power Supply: +1.8V
± 0.1V.
J7
VSSDL
-
DLL Ground.
J2
VREF
I
Reference voltage for inputs for SSTL interface.
Pin No.
Pin Name
I/O
Pin Function
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