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LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S

7 – 25

68

R0X0P

I

TMDS input port 0 data pairs.

67

R0X0N

I

70

R0X1P

I

69

R0X1N

I

72

R0X2P

I

71

R0X2N

I

66

R0XCP

I

TMDS input port 0 clock pair.

65

R0XCN

I

4

R1X0P

I

TMDS input port 1 data pairs.

3

R1X0N

I

6

R1X1P

I

5

R1X1N

I

8

R1X2P

I

7

R1X2N

I

2

R1XCP

I

TMDS input port 1 clock pair

1

R1XCN

I

14

R2X0P

I

TMDS input port 2 data pairs.

13

R2X0N

I

16

R2X1P

I

15

R2X1N

I

TMDS

T

X

CEC_A

37

CEC
Controller

CEC_D

60,61
58,59
56,57

DSDA1,
DSCL1

TMDS
DPLL/DEC

SCDT

HDCP REG

HDMI PORT PROCESSOR

43,
44

LOCAL
I2C

29
30

14,13
16,15
18,17

68,67
70,69
72,71

38

POWER_DOWN

HPD0
HPD1

PORT2

BOOTING
SEQUENCER

51

DSDA4,
DSCL4

CPI REG

62,63

39,
40

33,
34

HDCP ENGINE

22,21,
24,23,
26,25

PORT1

CSCL
CSDA

2,1

R0PWR5V
R1PWR5V
R2PWR5V
R3PWR5V
R4PWR5V

ALWAYS_ON

31
35

41
45

SiI9287

NV RAM

CONFIG
STATUS REG

INT

DSDA2,
DSCL2

48,
47

SBVCC

PORT0

HDMI DATAPATH

4,3
6,5
8,7

20,13

50

VCC33

52

TMDS

E

NC

32
36
42
46
49

OTP

9,27,64

EDID SRAM

DSDA3,
DSCL3

PORT3

R0X0P/N
R0X1P/N
R0X2P/N
R0XCP/N

12,11

54
53

66,65

MICOM_VCC33

DDC0
DDC1
DDC2
DDC3
DDC4

MHL Control

MHL
DP

DSDA0,
DSCL0

R1X0P/N
R1X1P/N
R1X2P/N
R1XCP/N

R2X0P/N
R2X1P/N
R2X2P/N
R2XCP/N

R3X0P/N
R3X1P/N
R3X2P/N
R3XCP/N

HPD2
HPD3

TX0P/N
TX1P/N
TX2P/N
TXCP/N

LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S

7 – 26

18

R2X2P

I

17

R2X2N

I

12

R2XCP

I

TMDS input port 2 clock pair

11

R2XCN

I

22

R3X0P

I

TMDS input port 3 data pairs.

21

R3X0N

I

24

R3X1P

I

23

R3X1N

I

26

R3X2P

I

25

R3X2N

I

20

R3XCP

I

TMDS input port 3 clock pair

19

R3XCN

I

60

TX0P

O

HDMI Tx Output port data.

61

TX0N

O

TMDS Low Voltage Differential Signal output data pairs.

58

TX1P

O

59

TX1N

O

56

TX2P

O

57

TX2N

O

62

TXCP

O

HDMI Output port Clock.

63

TXCN

O

TMDS Low Voltage Differential Signal output data pairs.

29

DSDA0

I/O

DDC I2C Data for respective port. 
These signals are true open drain, and do not pull-down to ground when power is not applied to the device.  
These pins require an external pull-up resistor.

33

DSDA1

I/O

39

DSDA2

I/O

43

DSDA3

I/O

30

DSCL0

I

DDC I2C Clock for respective port. 
These signals are true open drain, and do not pull-down to ground when power is not applied to the device.  
These pins require an external pull-up resistor.

34

DSCL1

I

40

DSCL2

I

44

DSCL3

I

32

R0PWR5V

 -

5-V Port detection input for respective port. 
Connect to 5-V signal from HDMI input connector.
These signals require a 10

Ω series resistor and at least a 1µ F capacitor to ground A 3.3kΩ pull-down resis-

tor is also required for these signals.

36

R1PWR5V

 -

42

R2PWR5V

 -

46

R3PWR5V

 -

31

CBUS_HPD0

O

Hot Plug Detect Output for respective port. 
Connect to HOTPLUG of HDMI input connector.In MHL mode, this serves at the respective port control bus.

35

CBUS_HPD1

O

41

CBUS_HPD2

O

45

CBUS_HPD3

O

49

R4PWR5V

 -

5V power from 5th Rx port.

54

CSCL

I

Local Configuration/Status I2C Clock. 
Chip configuration/status is accessed via this I2C port. This pin is a true open drain, so it does not pull to 
ground if power is not applied. 

53

CSDA

I/O

Local Configuration/Status I2C Data. 
Chip configuration/status is accessed via this I2C port. This pin is a true open drain, so it does not pull to 
ground if power is not applied.

48

DSCL4

I

DDC I2C Clock for VGA port.
These signals are true open drain, and do not pull-down to ground when power is not applied to the device. 
This pin requires an external pull-up resister.

47

DSDA4

I/O

DDC I2C Data for VGA port. 
These signals are true open drain, and do not pull-down to ground when power is not applied to the device. 
This pin requires an external pull-up resister.

55

TPWR_CI2CA

I/O

I2C Slave Address input/Transmit Power Sense Output. 
At the end of power -on-reset (POR), this pin is used as an input to latch the I2C sub-address. The level on 
this pin is latched when the POR transitions from the asscred state to the de-asserted state. After complec-
tion of POR, this pin is used as the TPWR output, indicating that the selected HDMI input port is receiving an 
active TMDS clock. This pin has an internal pull-up to the MICOMVCC33 power supply. If this signal is 
pulled-down, a 4.7L

Ω resister should be used. 

Note: There is a probability the POR logic may power up and not latch the level on this pin. A software 
workaround is required to determine the proper I2C slave address.

52

INT

O

Interrupt Output. 
This is an open_drain output and requires an external pull_up resister.

10

RSVD

 -

When SBVCC(pin38)=5V, RSVD pin #10 must be tied to GND with less than 10K resistor. When 
SBVCC(pin38)=3.3V, RSVD pin #10 must be tied to GND with 1M ohm resistor.

28

RSVD

 -

LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S

7 – 27

50

CEC_A

I/O

HDMI compliant CEC I/O used for interfacing to CEC devices. The signal is electrically compliant with CEC 
specification. This pin connects to the CEC signal of all HDMI connectors in the system. As an input, the pin 
acts as a LVTTL, Schmitt triggered input and is 5V tolerant. As an output, the pin acts as an NMOS driver 
with resistive pull-up. This pin has an internal pull-up resistor. 

51

CEC_D

I/O

CEC interface to local system.
This pin is an open drain and requires an external pull-up resister. This pin typically connects to a local CPU 
if the CEC functions are performed by the CPU directly, and not the CEC controller inside the device.

9,27,64

VCC33

 -

Analog and digital core VCC. Must be supplied at 3.3V

37

MICOM_VCC33

 -

During normal mode, this pin provides 3.3V power to external micro-controller. Maximum output current is 
30mA. This pin requires 1

µ F capacitor to ground.

38

SBVCC33

 -

3.3V standby power. If 3.3V standby mode is not used, this pin should be left as not connected.

ePad

Epad

 -

ePad must be connected to ground. All ground planes, analog and digital, must be tied together to the ePad, 
which must be connected to ground.

LC-32/40/46LE700E/RU/S,LU700E/S,LX700E/RU,LC-52LE700E/RU/S

7 – 28

1

GPIO9

I/O

General-purpose input/output port 9.

2

GPIO8

I/O

General-purpose input/output port 8.

3

TDI

I

GND

4

TDO

O

No operation

5

TRST

I

GND

6

TCK

I

No operation

7

TMS

I

GND

8

GPIO7

I/O

No operation

9

N_RESET

I

Hardware reset, active Low.

10

VDD

supply

Power supply (3.3V)

11

GND

supply

GND

12

VDD_IO_3V3

supply

3.3V

13

GPIO6/CS1

I/O

General-purpose input/output port 6.

14

GPIO5/CS0

I/O

General-purpose input/output port 5.

15

SDA

I/O

I2C serial data

16

SCL

I

I2C serial clock

17

TS_CKOUT

O

TS_CLOCK

18

TS_SYNC

O

TS_SYNC

19

TS_VAL

O

TS_Data Valid

20

TS_ERR

O

TS_Packet Error

21

TS_DATA[0]

O

TS_DATA0

22

TS_DATA[1]

O

TS_DATA1

23

TS_DATA[2]

O

TS_DATA2

STV0297E

ADC

Demodulator is a complete QAM (quadrature amplitude modulation)demodulation
and FEC (forward error correction) solution

I2C Repeater

Lock status
IT generator

INP

INM

GPIO/LOCK

AGC and
delayed AGC

Derotator

Adjacent channels
removal filter

Symbol timing recovery
and Nyquist filtering

Carrier loop recovery

Equalizer

Phase noise canceller

FEC Annex A and C
De-interleaver
Reed - Solomon FEC decoder
Descrambler

Signal quality
estimator
BER Tester

TSMF function

JTAG
controller

I2C interface

to all blocks

GPIO

switching

matrix

GPIO/AGC2

GPIO/AGC1

GPIO/IT

GPIO/SDAT

N_RESET

GPIO

GPIO/CS0

GPIO/SCLT

GPIO/CS1

GPIO

Clock
generator

Output
formatter

TS_DATA[0:7]

TS_CKOUT

TCK

TRST

SDA

TS_SYNC

SCL

Z0

A

TDO

TS_VAL

TS_ERR

TDI

TMS