Sharp LC-40LE600E (serv.man8) Service Manual ▷ View online
LC-32/40/46LE600E/RU/S
6 – 17
2.12.2 Pin Connections and short description
2.13. IC8455 (VHiBR24S64F-1Y)
This IC is a block diagram and description LC-32A47E/RU/V (S59Z4LC32A47E) please see the service manual.
Pin No.
Pin Name
I/O
Pin Function
29-44
IO0-IO7
I/O
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read/program opera-
tions.
The inputs are latched on the rising edge of Write Enable (WE#).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
The IO pins allow to input command, address and data and to output data during read/program opera-
tions.
The inputs are latched on the rising edge of Write Enable (WE#).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
16
CLE
I
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
17
ALE
I
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
9
CE#
I
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.
This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.
18
WE#
I
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge
of WE#.
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge
of WE#.
8
RE#
I
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
REA after the falling edge of RE# which also increments the internal column address counter by one.
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
REA after the falling edge of RE# which also increments the internal column address counter by one.
19
WP#
I
WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program/erase)
operations.
The WP# pin, when Low, provides an Hardware protection against undesired modify (program/erase)
operations.
7
A/B#
I
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
37
VCC
—
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
The VCC supplies the power for all the operations (Read, Write, Erase).
36
VSS
—
GROUND
1-6, 10-11, 14-15,
20-28, 33-35,
39-40, 45-48
20-28, 33-35,
39-40, 45-48
NC
—
NO CONNECTION
LC-32/40/46LE600E/RU/S
6 – 18
2.14. IC4402 (VHiAOZ1320C-1Y)
2.14.1 Block Diagram
2.14.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
1
OUT
O
Output.
OUT is the source of the P-channel MOSFET.
OUT is the source of the P-channel MOSFET.
2
GND
—
Ground
3
EN
I
Enable.
The P-channel MOSFET turns on when EN is logic HIGH.
The P-channel MOSFET turns on when EN is logic HIGH.
4
NC
—
No connect.
This pin is not internally connected.
This pin is not internally connected.
5
GND
—
Ground
6
IN
I
Input.
IN is the drain of the P-channel MOS FET. It is the supply input of the IC.
IN is the drain of the P-channel MOS FET. It is the supply input of the IC.
LC-32/40/46LE600E/RU/S
6 – 19
2.15. IC4401 (VHiMT8295AE-1Q)
2.15.1 Block Diagram
2.15.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Miscellaneous
107
RESETB
I
Chip reset.
CI_CNT_RESET
114
CI_INT
O
interrupt.
CI_CNT_INT
NAND flash
116
CI_DATA0
I/O
NAND Flash Data bit 0.
PDD0_
115
CI_DATA1
I/O
NAND Flash Data bit 1.
PDD1_
95
CI_DATA2
I/O
NAND Flash Data bit 2.
PDD2_
102
CI_DATA3
I/O
NAND Flash Data bit 3.
PDD3_
101
CI_DATA4
I/O
NAND Flash Data bit 4.
PDD4_
100
CI_DATA5
I/O
NAND Flash Data bit 5.
PDD5_
99
CI_DATA6
I/O
NAND Flash Data bit 6.
PDD6_
98
CI_DATA7
I/O
NAND Flash Data bit 7.
PDD7_
94
CI_CEB
I
NAND Flash Chip enable.
CI_CE#
LC-32/40/46LE600E/RU/S
6 – 20
106
CI_RB
O
NAND Flash Ready.
N_PARB_
96
CI_WEB
I
NAND Flash Write enable.
XEWE_
103
CI_ALE
I
NAND Flash Address Latch enable.
PAALE_
105
CI_CLE
I
NAND Flash Command Latch enable.
PACLE_
117
CI_OEB
I
NAND Flash Output enable.
XERE_
CLK/Crystal
109
XTALO
O
Crystal output.
XTAL_O
110
XTALI
I
Crystal input.
XTAL_I
Transport stream (TS)
6
TOCLK
I
Transport stream 1 input clock.
TS_CPUOUT_CLK
7
TOSYNC
I
Transport stream 1 input sync.
TS_CPUOUT_SYNC
8
TOVALID
I
Transport stream 1 input valid.
TS_CPUOUT_VAL
9
TODATA0
I
Transport stream 1 input data bit 0.
TS_CPUOUT_DO
11
TODATA1
I
Transport stream 1 input data bit 1.
Transport stream 2 input clock.
Transport stream 2 input clock.
open
12
TODATA2
I
Transport stream 1 input data bit 2.
Transport stream 2 input sync.
Transport stream 2 input sync.
open
13
TODATA3
I
Transport stream 1 input data bit 3.
Transport stream 2 input valid.
Transport stream 2 input valid.
open
14
TODATA4
I
Transport stream 1 input data bit 4.
Transport stream 2 input data.
Transport stream 2 input data.
open
16
TODATA5
I
Transport stream 1 input data bit 5.
open
17
TODATA6
I
Transport stream 1 input data bit 6.
open
18
TODATA7
I
Transport stream 1 input data bit 7.
open
123
TS_CKO
O
Transport stream output clock.
TS_CPUIN_CLK
125
TS_SYNCO
O
Transport stream output sync.
TS_CPUIN_SYNC
122
TS_VALIDO
O
Transport stream output valid.
TS_CPUIN_VAL
124
TS_DATAO
O
Transport stream output data.
TS_CPUIN_DO
General Purpose Input and Output (GPIO)
1
GPIO0
I/O
General purpose I/O bit 0. (Resister-Ground)
R-G
2
GPIO1
I/O
General purpose I/O bit 1. (Resister-Ground)
R-G
3
GPIO2
I
General purpose I/O bit 2. (Head Phone Plug)
HP_PLUG
4
GPIO3
O
General purpose I/O bit 3. (Amp Standby)
AMP_STBY
19
GPIO4
I/O
General purpose I/O bit 4.
open
20
GPIO5
O
General purpose I/O bit 5. (Antena_5V_SW)
ANT_5V_SW
21
GPIO6
I/O
General purpose I/O bit 6.
open
91
GPIO7
I/O
General purpose I/O bit 7.
open
92
GPIO8
I/O
General purpose I/O bit 8.
open
93
GPIO9
O
General purpose I/O bit 9. (Common Interface VCC Enable)
CI_VCCEN
118
GPIO10
O
General purpose I/O bit 10. (Panel I2C Enable)
PNL_I2C_EN
119
GPIO11
O
General purpose I/O bit 11. (Panel Write Protect)
PNL_WP
120
GPIO12
I
General purpose I/O bit 12. (232C_Eable)
232C_EN
127
GPIO13
O
General purpose I/O bit 13. (ATV_Power_SW)
ATV_POW_SW
128
GPIO14
I
General purpose I/O bit 14. (Interrupt enable _SW)
IREM_SW
PCMCIA/CI
83
D0
I/O
PCMCIA data bit 0.
C_D0
85
D1
I/O
PCMCIA data bit 1.
C_D1
87
D2
I/O
PCMCIA data bit 2.
C_D2
24
D3
I/O
PCMCIA data bit 3.
C_D3
26
D4
I/O
PCMCIA data bit 4.
C_D4
28
D5
I/O
PCMCIA data bit 5.
C_D5
30
D6
I/O
PCMCIA data bit 6.
C_D6
32
D7
I/O
PCMCIA data bit 7.
C_D7
81
D8
I/O
PCMCIA data bit 8.
TS_CIOUT_D0
84
D9
I/O
PCMCIA data bit 9.
TS_CIOUT_D1
86
D10
I/O
PCMCIA data bit 10.
TS_CIOUT_D2
25
D11
I/O
PCMCIA data bit 11.
TS_CIOUT_D3
27
D12
I/O
PCMCIA data bit 12.
TS_CIOUT_D4
29
D13
I/O
PCMCIA data bit 13.
TS_CIOUT_D5
31
D14
I/O
PCMCIA data bit 14.
TS_CIOUT_D6
34
D15
I/O
PCMCIA data bit 15.
TS_CIOUT_D7
80
A0
O
PCMCIA address bit 0.
CI_A0
78
A1
O
PCMCIA address bit 1.
CI_A1
75
A2
O
PCMCIA address bit 2.
CI_A2
73
A3
O
PCMCIA address bit 3.
CI_A3
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Click on the first or last page to see other LC-40LE600E (serv.man8) service manuals if exist.