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LC-32/40/46LE600E/RU/S

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J8, K8

CK, CK#

I

Clock:
CK and CK# are differential clock inputs. All address and control input signals are sampled on the 
crossing of the positive edge of CK and negative edge of CK#.
Output (read) data is referenced to the crossings of CK and CK# (both directions of crossing).

K2

CKE

I

Clock Enable: 
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and 
output drivers.
Taking CKE Low provides Pre charge Power-Down and Self Refresh operation (all bank idle), or 
Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchro-
nous for self refresh exit.
After VREF has become stable during the power on and initialization sequence, it must be main-
tained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must 
be maintained to this input. 
CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, 
CK#, ODT and CKE are disabled during power-down. Input buffers, excluding CKE are disabled 
during self refresh. 

L8

CS#

I

Chip Select:
All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks.
CS# is considered part of the command code.

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K9

ODT

I

On Die Termination:
ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM.
When enabled, ODT is only applied to each DQ, DQS, DQS#, RDQS, RDQS#, and DM signal for 
x4/x8 configuration. 
For x16 configuration, ODT is applied to each DQ, UDQS/UDQS#.
LDQS/LDQS#, UDM and LDM signal. 
The ODT pin will be ignored if the Extended Mode Register Set (EMRS) is programmed to disable 
ODT.

K7, L7, K3

RAS#, CAS#, 
WE#

I

Command Inputs:
RAS#, CAS# and WE# (along with CS#) define the command being entered.

F3, B3

DM
(UQM3) (DQM1)
   or
(UQM2) (DQM3)

I

Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches 
the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS# is enabled by EMRS 
command.

L2, L3

BA0, BA1

I

Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Pre charge command is being 
applied.
Bank address also determines if the mode register or extended mode register is to be accessed 
during a MRS or EMRS cycle.

M8, M3, M7, N2, 
N8, N3, N7, P2, 
P8, P3, M2, P7, 
R2

A [0:12]

I

Address Inputs: Provide the row address for Active commands, and the column address and Auto 
Pre charge bit for Read/Write commands to select one location out of the memory array in the 
respective bank. 
A10 is sampled during a pre charge command to determine whether the PRECHARGE applies to 
one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be pre charged, the bank is selected by BA0, BA1. The address inputs also 
provide the op-code during a Mode Register Set command. 

G8, G2, H7, H3, 
H1, H9, F1, F9, 
C8, C2, D7, D3, 
D1, D9, B1, B9

DQ [0:15]
   or
DQ [16:31]

I/O

Data Input/Output: Bi-directional data bus.

B7, A8, F7, E8

(DQS1), (DQS1#)
(DQS0), (DQS0#)
    or
(DQS3), (DQS3#)
(DQS2), (DQS2#)

I/O

Data Strobe: 
Output with read data, input with write data. Edge-aligned with read data, centered in write data. 
For the x16, DQS1 corresponds to the data on DQ0>DQ7; DQS0 corresponds to the data on 
DQ8>DQ15.
For the x8, an DQS2 option using DM pin can be enabled via the EMRS (1) to simply read timing.
The data strobes DQS1, DQS0, DQS3, and DQS2 may be used in single ended mode or paired 
with optional complementary signals DQS1#, DQS0#, DQS3# and DQS2# to provide differential 
pair signaling to the system during both reads and writes. A control bit at EMRS (1) [A10] enables 
or disables all complementary data strobe signals.
In this data sheet, “differential DQS signals” refers to any of the following with A10=0 of EMRS (1)
x4   DQS1/DQS1#
x8   DQS1/DQS1# if EMRS (1) [A11] =0
x8   DQS1/DQS1#, DQS2/DQS2#
x16 DQS0/DQS0# and DQS3/DQS3#

A2, E2, L1, R3, 
R7, R8

NC

—

No Connect: No internal electrical connection is present.

A1, E1, J9, M9, 
R1

VDD

—

Power Supply: +1.8V 

± 0.1V. 

A9, C1, C3, C7, 
C9, E9, G1, G3, 
G7, G9

VDDQ

—

DQ Power Supply: +1.8V 

± 0.1V.

A3, E3, J3, N1, 
P9

VSS

—

Ground.

A7, B2, B8, D2, 
D8, E7, F2, F8, 
H2, H8

VSSQ

—

Ground. DQ Ground.

J1

VDDL

—

DLL Power Supply: +1.8V 

± 0.1V. 

J7

VSSDL

—

DLL Ground.

J2

VREF

I

Reference voltage for inputs for SSTL interface.

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1

CS#
(Chip Select)

I

Places device in active power mode when driven low. 
Deselects device and places SO at high impedance when high. 
After power-up, device requires a falling edge on CS# before any command is written. 
Device is in standby mode when a program, erase, or Write Status Register operation is not in progress.

2

SO
(Signal data Output)

O

Transfers data serially out of the device on the falling edge of SCK.

3

W#
(Write Protect)

I

Protects the memory area specified by Status Register bits BP2:BP0. 
When driven low, prevents any program or erase command from altering the data in the protected mem-
ory area.

4

GND

—

Ground

5

SI
(Serial Data Input)

I

Transfers data serially into the device. Device latches commands, addresses, and
program data on SI on the rising edge of SCK.

6

SCK
(Serial Clock)

I

Provides serial interface timing. 
Latches commands, addresses, and data on SI on rising edge of SCK. 
Triggers output on SO after the falling edge of SCK.

7

HOLD#

I

Pauses any serial communication with the device without deselecting it. When driven low, SO is at high 
impedance, and all input at SI and SCK are ignored. Requires that CS# also be driven low.

8

VCC

—

Supply Voltage

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