DOWNLOAD Sharp LC-40LE531E (serv.man2) Service Manual ↓ Size: 23.65 MB | Pages: 127 in PDF or view online for FREE

Model
LC-40LE531E (serv.man2)
Pages
127
Size
23.65 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
lc-40le531e-sm2.pdf
Date

Sharp LC-40LE531E (serv.man2) Service Manual ▷ View online

45
LC-32LE511
LC-40LE511
LC-40LE531
LC-32LE511
LC-40LE511
LC-40LE531
28
The EM68B16C is a high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous 
dynamic random-access memory (SDRAM) containing 512 Mbits in a 16-bit wide data I/Os. 
It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os The 
device is designed to comply with DDR2 DRAM key features such as posted CAS# with  
additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance 
adjustment, and On Die Termination(ODT). All of the control and address inputs are 
synchronized with a pair of externally supplied differential clocks. Inputs  are latched at the 
cross point of differential clocks (CK rising and CK# falling) All I/Os are synchronized with a 
pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address 
bus is used to convey row, column, and bank address information in RAS #, CAS# 
multiplexing style. Accesses begin with the registration of a Bank Activate command, and 
then it is followed by a Read or Write command. Read and write accesses to the DDR2 
SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a 
programmed number of  locations in a programmed sequence.  Operating the four memory 
banks in an interleaved fashion allows random access operation to occur at a higher rate than 
is possible with standard DRAMs. An auto precharge function may be enabled to provide a 
self-timed row precharge that is initiated at the end of the burst sequence. A sequential and  
gapless data rate is possible depending on burst length, CAS# latency, and speed grade of the 
device. 
b) Pinning
46
LC-32LE511
LC-40LE511
LC-40LE531
29
10.
4Gbit NAND Flash Memory (U35)
ST  NAND04G-B2D
a) Key Features
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– Up to 8 Gbit memory array
– Cost-effective solution for mass storage 
applications
����������������
– x8 or 16x bus width
– Multiplexed address/data
���������������������������������������
�����������
– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words
������������
– x8 device: (128K + 4 K spare) bytes
– x16 device: (64K + 2 K spare) words
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– Array split into two independent planes
– Program/erase operations can be 
performed on both planes at the same time
�������������������
– Random access: 25 μs (max)
– Sequential access: 25 ns (min)
– Page program time: 200 μs (typ)
– Multiplane page program time (2 pages): 
200 μs (typ)
�����������������������������������������
detection code (EDC)
�����������������
������������������
– Block erase time: 1.5 ms (typ)
– Multiblock erase time (2 blocks): 
1.5 ms (typ)
�����������������
����������������������
��������������������������
����������������������
��������������������������������
– Up to 8 Gbit memory array
– Cost-effective solution for mass storage 
applications
������������face
– x8 or 16x bus width
– Multiplexed address/data
���������������������������������������
�����������
– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words
������������
– x8 device: (128K + 4 K spare) bytes
– x16 device: (64K + 2 K spare) words
�������������������������
– Array split into two independent planes
– Program/erase operations can be 
performed on both planes at the same time
�������������������
– Random access: 25 μs (max)
– Sequential access: 25 ns (min)
– Page program time: 200 μs (typ)
– Multiplane page program time (2 pages): 
200 μs (typ)
�����������������������������������������
detection code (EDC)
�����������������
������������������
– Block erase time: 1.5 ms (typ)
– Multiblock erase time (2 blocks): 
1.5 ms (typ)
�����������������
����������������������
��������������������������
���������������������n
47
LC-32LE511
LC-40LE511
LC-40LE531
LC-32LE511
LC-40LE511
LC-40LE531
30
b) Pinning
48
LC-32LE511
LC-40LE511
LC-40LE531
31
11.
128Mbit NAND Flash Memory (U17)
ST  NAND128-A
a) Key Features
��������������������������
MEMORIES
– Up to 1 Gbit memory array
– Up to 32 Mbit spare area
– Cost effective solutions for mass storage 
applications
����������������
– x8 or x16 bus width
– Multiplexed Address/ Data
– Pinout compatibility for all densities
����������������
– 1.8V device: VDD = 1.7 to 1.95V
– 3.0V device: VDD = 2.7 to 3.6V
�����������
– x8 device: (512 + 16 spare) Bytes
– x16 device: (256 + 8 spare) Words
������������
– x8 device: (16K + 512 spare) Bytes
– x16 device: (8K + 256 spare) Words
���������������������
– Random access: 12μs (max)
– Sequential access: 50ns (min)
– Page program time: 200μs (typ)
������������������������
– Fast page copy without external 
buffering
������������������
– Block erase time:  2ms (Typ)
�����������������
����������������������
���������������������������
OPTION
– Simple interface with microcontroller
����������������������
��������������������������
– Program/Erase locked during Power 
Transitions
����������������
– 100,000 Program/Erase cycles
– 10 years Data Retention
�����������������
– Lead-Free Components are Compliant 
with the RoHS Directive
�������������������
– Error Correction Code software and 
hardware models
– Bad Blocks Management and Wear 
Leveling algorithms
– File System OS Native reference 
software
– Hardware simulation models
b) Pinning
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