Sharp LC-40LE531E (serv.man2) Service Manual ▷ View online
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The BCM3556 supports direct PC inputs up to UXGA 1600x1200 formats with autophase
and automode detection and supports dual LVDS outputs to support 1080p60 panels.
The BCM3556 integrates a 400-MHz 32-bit MIPS dual CPU with two 32-KB
instructioncaches and a combined 64-KB data cache with a 128-KB L2 cache, and a 32-bit
800/1066-MHz DDR2. The BCM3556 also supports an 8-bit external NAND Flash interface
and SPI Flash interface for booting. Integrated peripherals include two USB2.0 ports, three
UARTs, controllers for SPI, BSC, keypad, LED and IR Tx/Rx, and an Ethernet port with
MAC and integrated PHY.
The BCM3556 is available in several package options: WXGA and FHD, PIP and non-PIP, or
MPEG-only and combined AVC/MPEG-2.
b) Features
• Advanced multiformat decoder supporting the following:
- H.264/AVC Main and High Profile to Level 4.1 (HD), Level 3.1 (SD)
- HD/SD AVS Jizhun Profile Levels 2.0, 4.0, and 6.0
- VC-1 Advanced Profile @ Level 3, simple and main profiles
- HD/SD MPEG-2 Main Profile at Main and High levels
- MPEG still image decode
- HD DivX® 3.11/4.11/5.x/6x/Home Theater
• 3D/2D OpenGL® ES 1.0- compliant graphics core
• Integrated Video Processing:
- 3D Color management
- Digital, Analog, and Mosquito Noise Reduction
- 1080i motion adaptive deinterlacing with 3:2/2:2 pull-down
- True 10-bit video carried through system
• Dual HDMI 1.3a receivers
• Extensive audio support:
- AAC+ Level 2, AAC-HE
- Dolby® Digital, Dolby Digital Plus, Trusurround XT®
- MPEG I layers 1, 2, and 3 (MP3)
- Windows Media® and Windows Media Pro audio
- Audio DACs, input switch, and equalizer
• Ethernet MAC and PHY
• Integrated DVB-T COFDM terrestrial demodulator:
- Standards compliance: ETSI EN 300 744, Nordig Unified v1.0.3, DTG D-Book 5
compliant
- Excellent Doppler performance
- Active impulse noise suppression
• Integrated PAL/SECAM Demodulator
• PAL decoder with a 3D/2D comb
• Direct PC input support up to 1600 x 1200 UXGA
• Integrated dual-link LVDS transmitters
• Dual USB 2.0
• A 400-MHz 32-bit MIPS dual CPU with two 32-KB instruction caches and a combined 64
KB data cache with 128-KB L2 cache
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c) BCM3556 - Block Diagram
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6. VIDEO BACK-END PROCESSOR (Trident)
PNX5120EH
a) General Description
The PNX5120EH is an advanced video picture improvement IC and the world's first solution,
NXP’s Motion Accurate Picture Processing (MAPP), to combine movie judder cancellation,
motion sharpness and vivid color management in a single device. Aimed primarily at digital
and hybrid flat panel televisions in the mid-end and high-end European,Asian and U.S.
consumer markets, it complies with relevant industry standards.LCD TVs represent a huge
and growing market, and the PNX5120EH offers manufacturers a unique combination of
richer color, dynamic motion, sensational sharpness, deep contrast, and full HD resolution.
Moreover, you can easily tailor that balance via the Automatic Picture Control tool (delivered
by NXP as part of a separate System Design-in Toolkit) to meet your own image quality
requirements.
b) Features
Single 27 MHz crystal clock input for all internal generated clocks
Three TriMedia TM3271 400 MHz, 32-bit VLIW media-processing cores with:
o five instructions per clock cycle
o 32 kB instruction cache
o 64 kB data cache
Integrated DDR2 SDRAM controller, 32-bit wide, up to 366 MHz clock (DDR2-800),
supporting 32 MB, 64 MB, 128 MB, and 256 MB single-rank memory configurations
Separately licensed, the PNX5120EH comes with an easy-to-use System Design-in
Toolkit (SDT), which includes the NXP Picture Quality Tuning Tool, firmware image
containing the NXP proprietary Picture Improvement features, and GPL-licensed U-
Boot Bootloader software.
DDR2-400 to DDR2-800 data rates supported
PCI/XIO (V2.2) operating at 33 MHz
Two UARTs
Two I2C DMA interfaces (100 kHz/400 kHz); the second I2C can be used as a
debugging interface
16 GPIO pins
Five PWM outputs
Support for 8-bit NOR flash up to 64 MB
Support for 8-bit/16-bit NAND flash up to 128 MB
c) PNX5120EH - Block Diagram
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7. FPGA (Spartan-3E)
XC3S1200E
a) General Description
The Spartan™-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically
designed to meet the needs of high volume, cost-sensitive consumer electronic applications.
The five-member family offers densities ranging from 100,000 to 1.6 million system gates,
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