Sharp LC-40LE361E Service Manual ▷ View online
49
LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
Table 10: Recommended operating conditions
6. 1GB G-DIE DDR3 SDRAM
Samsung K4B1G1646G
a. Key Features
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for
1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin 900MHz fCK for 1866Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8
• Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,13
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8
(DDR31600) and 9 (DDR3-1866)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with
tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal (self) calibration: Internal self-calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C •
• Internal (self) calibration: Internal self-calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C •
Asynchronous Reset
• Package : 96 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
50
LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
Table 11: 1Gb DDR3 G-die Speed bins
b. Description
The 1Gb DDR3 SDRAM G-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks
device. This synchronous device achieves high speed double-data-rate transfer rates of up to
1866Mb/sec/pin (DDR3- 1866) for general applications.
1866Mb/sec/pin (DDR3- 1866) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-tures such as posted CAS,
Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous
Reset.
Reset.
All of the control and address inputs are synchronized with a pair of exter-nally supplied differential
clocks. Inputs are latched at the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are
synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The
address bus is used to convey row, column, and bank address information
synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The
address bus is used to convey row, column, and bank address information
in a RAS/CAS multiplexing
style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V
VDDQ. The 1Gb DDR3 G-die device is available in 78ball FBGAs(x4/x8).
VDDQ. The 1Gb DDR3 G-die device is available in 78ball FBGAs(x4/x8).
Table 12: Absolute Maximum DC Ratings
Table 13: Recommended operating conditions
51
LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
7. 2GBIT (256M X 8 BIT) NAND FLASH MEMORY
H27U2G8F2CTR-BC
a. Key Features
DENSITY
- 2Gbit: 2048blocks
Nand FLASH INTERFACE
- NAND Interface
- ADDRESS / DATA Multiplexing
SUPPLY VOLTAGE
- Vcc = 3.0/1.8V Volt core supply voltage for Program,
Erase and Read operations.
MEMORY CELL ARRAY
- X8: (2K + 64) bytes x 64 pages x 2048 blocks
- X16: (1k+32) words x 64 pages x 2048 blocks
PAGE SIZE
- X8: (2048 + 64 spare) bytes
- X16:(1024 + 32spare) Words
Block SIZE
- X8: (128K + 4K spare) bytes
- X16:(64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 25us (Max)
- Sequential access: 25ns / 45ns (3.0V/1.8V, min.)
- Program time(3.0V/1.8V): 200us / 250us (Typ)
- Multi-page program time (2 pages):
200us / 250us (3.0V/1.8V, Typ.)
BLOCK ERASE / MULTIPLE BLOCK ERASE
- Block erase time: 3.5 ms (Typ)
- Multi-block erase time (2 blocks):
3.5ms/ 3.5ms (3.0V/1.8V, Typ.)
SECURITY
- OTP area
- Serial number (unique ID)
- Hardware program/erase disabled during Power transition
- Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available, having program and erase time.
- Single and multiplane copy back program with automatic EDC (error detection code)
- Single and multiplane page re-program
- Single and multiplane cache program
- 2Gbit: 2048blocks
Nand FLASH INTERFACE
- NAND Interface
- ADDRESS / DATA Multiplexing
SUPPLY VOLTAGE
- Vcc = 3.0/1.8V Volt core supply voltage for Program,
Erase and Read operations.
MEMORY CELL ARRAY
- X8: (2K + 64) bytes x 64 pages x 2048 blocks
- X16: (1k+32) words x 64 pages x 2048 blocks
PAGE SIZE
- X8: (2048 + 64 spare) bytes
- X16:(1024 + 32spare) Words
Block SIZE
- X8: (128K + 4K spare) bytes
- X16:(64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 25us (Max)
- Sequential access: 25ns / 45ns (3.0V/1.8V, min.)
- Program time(3.0V/1.8V): 200us / 250us (Typ)
- Multi-page program time (2 pages):
200us / 250us (3.0V/1.8V, Typ.)
BLOCK ERASE / MULTIPLE BLOCK ERASE
- Block erase time: 3.5 ms (Typ)
- Multi-block erase time (2 blocks):
3.5ms/ 3.5ms (3.0V/1.8V, Typ.)
SECURITY
- OTP area
- Serial number (unique ID)
- Hardware program/erase disabled during Power transition
- Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available, having program and erase time.
- Single and multiplane copy back program with automatic EDC (error detection code)
- Single and multiplane page re-program
- Single and multiplane cache program
- Cache read
- Multiplane block erase Reliability
- 100,000 Program / Erase cycles (with 1bit /528Byte ECC)
- 10 Year Data retention
ONFI 1.0 COMPLIANT COMMAND SET ELECTRONICAL SIGNATURE
-
Maunufacture ID: ADh
- Device ID
PACKAGE
- Lead/Halogen Free
- TSOP48 12 x 20 x 1.2 mm
- FBGA63 9 x 11 x 1.0 mm
52
LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
b. Description
H27 (U_S)2G8_6F2C series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.0/1.8 Vcc
Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the
solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible
to preserve valid data while old data is erased.
solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible
to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. Memory array is split into 2 planes, each of them
consisting of 1024 blocks. Like all other 2KB - page NAND Flash devices, a program operation allows to write the
2112-byte page in typical 200us(3.3V) and an erase operation can be performed in typical 3.5ms on a 128Kbyte
block. In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a time (one per each
plane) or to erase 2 blocks at a time (again, one per each plane). As a consequence, multi-plane architecture allows
program time to be reduced by 40% and erase time to be reduction by 50%. In case of multi-plane operation, there is
small degradation at 1.8V application in terms of program/erase time. The multiplane operations are supported
both with traditional and ONFI 1.0 protocols. Data in the page can be read out at 25ns (3V version) and 45ns (1.8V
version) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. This interface allows a reduced pin count and easy migration towards different densities, without any
rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE
and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including
pulse repetition, where required, and internal verification and margining of data. A WP# pin is available to provide
hardware protection against program and erase operations.
2112-byte page in typical 200us(3.3V) and an erase operation can be performed in typical 3.5ms on a 128Kbyte
block. In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages at a time (one per each
plane) or to erase 2 blocks at a time (again, one per each plane). As a consequence, multi-plane architecture allows
program time to be reduced by 40% and erase time to be reduction by 50%. In case of multi-plane operation, there is
small degradation at 1.8V application in terms of program/erase time. The multiplane operations are supported
both with traditional and ONFI 1.0 protocols. Data in the page can be read out at 25ns (3V version) and 45ns (1.8V
version) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. This interface allows a reduced pin count and easy migration towards different densities, without any
rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE
and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including
pulse repetition, where required, and internal verification and margining of data. A WP# pin is available to provide
hardware protection against program and erase operations.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with
multiple memories the RB# pins can be connected all together to provide a global status signal. Each block can be
programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of Nand
Flash devices, the implementation of an ECC is mandatory. The chip supports CE# don't care function. This
function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since
the CE# transitions do not stop the read operation. In addition, device supports ONFI 1.0 specification.
programmed and erased up to 100,000 cycles with ECC (error correction code) on. To extend the lifetime of Nand
Flash devices, the implementation of an ECC is mandatory. The chip supports CE# don't care function. This
function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since
the CE# transitions do not stop the read operation. In addition, device supports ONFI 1.0 specification.
The copy back function allows the optimization of defective blocks management: when a page program
operation fails the data can be directly programmed in another page inside the same array section without the time
consuming serial data insertion phase. Copy back operation automatically executes embedded error detection
operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of every 264-word (x16) can be detected. With this
feature it is no longer necessary to use an external to detect copy back operation errors. Multiplane copy back is also
supported, both with traditional and ONFI 1.0 protocols. Data read out after copy back read (both for single and
multiplane cases) is allowed. In addition, Cache program and multi cache program operations improve the
programing throughput by programing data using the cache register.
consuming serial data insertion phase. Copy back operation automatically executes embedded error detection
operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of every 264-word (x16) can be detected. With this
feature it is no longer necessary to use an external to detect copy back operation errors. Multiplane copy back is also
supported, both with traditional and ONFI 1.0 protocols. Data read out after copy back read (both for single and
multiplane cases) is allowed. In addition, Cache program and multi cache program operations improve the
programing throughput by programing data using the cache register.
The devices provide two innovative features: page re-program and multiplane page re program. The page re-
program allows to re-program one page. Normally, this operation is performed after a previously failed page
program operation. Similarly, the multiplane page re-program allows to re-program two pages in parallel, one per
each plane. The first page must be in the first plane while the second page must be in the second plane; the
multiplane page re-program operation is performed after a previously failed multiplane page program operation. The
page re-program and multiplane page re-program guarantee improve performance, since data insertion can be
omitted during re-program operations, and save ram buffer at the host in the case of program failure. The devices,
available in the TSOP48 (12X20mm) package, support the ONFI1.0 specification and come with four security
features:
- OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored
permantely.
- Serial number (unique identifier), which allows the devices to be uniquely identified.
-Read ID2 extension
program operation. Similarly, the multiplane page re-program allows to re-program two pages in parallel, one per
each plane. The first page must be in the first plane while the second page must be in the second plane; the
multiplane page re-program operation is performed after a previously failed multiplane page program operation. The
page re-program and multiplane page re-program guarantee improve performance, since data insertion can be
omitted during re-program operations, and save ram buffer at the host in the case of program failure. The devices,
available in the TSOP48 (12X20mm) package, support the ONFI1.0 specification and come with four security
features:
- OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored
permantely.
- Serial number (unique identifier), which allows the devices to be uniquely identified.
-Read ID2 extension
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, no described in the
datasheet. For more details about them, contact your nearest Hynix sales office.
Click on the first or last page to see other LC-40LE361E service manuals if exist.