Sharp LC-40LE361E Service Manual ▷ View online
45
LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
Hardware JPEG
Supports sequential mode, single scan.
Supports both colour and grayscale pictures.
Following the file header scan the hardware
decoder fully handles the decode process.
Supports programmable Region of Interest
(ROI).
Supports formats: 422/411/420/444/422T.
Supports scaling down ratios: 1/2, 1/4, 1/8.
Supports picture rotation.
NTS/PAL/SECAM Video Decoder
Supports NTSC-M, NTSC-1, NTSC-4, 43, PAL (B,
D, G, H, N, I, Nc) and SECAM standards.
Automatic standard detection.
Motion adaptive 3D comb filter.
Four configurable CVBS & Y/C S-video inputs.
Supports Teletext, Closed Caption ( analog CC
608/ analog CC 708/digital CC 608/ digital CC
708), V-chip and SCTE.
708), V-chip and SCTE.
Multi-Standard TV Sound Processor
.
SIF audio decoding.
Supports BTSC/A2/ETA-J demodulation.
Supports NICAM/FM/AM demodulation.
Supports MTS Mode Mono/Stereo/SAP in
BTSC/ ETA-J Mode.
Supports Mono/Stereo/Dual in A2/NICAM
mode.
Built-in audio sampling rate conversion (SRC).
Audio processing for loudspeaker channel,
including volume, valance, mute, tone, EQ,
virtual stereo/surround and treble/bass
controls.
virtual stereo/surround and treble/bass
controls.
Advanced sound processing option available,
for example: Dolby
1
, SRS
2
, BBE
3
, QSound
4
,
Auyssey
5
.
Supports digital audio format decoding.
-
MPEG-1, MPEG-2 (Layer I/II), MP3, Dolby
Digital (AC-
Optional
, AAC-LC, HE-AAC, WMA,
and WMA9 Pro.
-
Supports
Optional
Doby Digital Plus, Dolby
pulse, and MS0 multistream decoder,
including Dolby Digital Encoder for
transcoding streams to Dolby Digital
5.1(DDCO).
including Dolby Digital Encoder for
transcoding streams to Dolby Digital
5.1(DDCO).
Supports MPEG Audio, Dolby Digital, Dolby
Digital Plus, HE-AAC format AD (Audio
Description) .
Description) .
Support MPEG audio encoding.
Supports time-shifting PVR.
Audio Interface.
One SIF audio input interface with minimal
external saw filter.
Six L/R audio line- inputs.
Three L/R outputs for main speakers and
additional TV line-outputs.
One embedded stereo headphone driver.
I2S digital audio output.
S/PDIF digital audio output & input.
HDMI
6
audio channel processing.
Programmable delay for audio/video
synchronization.
Analog RGB Compliant Input Ports.
Three analog port support up to 1080P.
Supports PC RGB input up to SXGA@75Hz.
Supports HDTV RGB/YPbPr/YCbCr.
Supports Composite Sync and SOG Sync-on-
Green.
Automatic colour calibration.
Analogue RGB Auto-Configuration & Detection.
Auto Input signal format and mode detection.
Auto-Running function including phasing,
positioning, offset, gain and jitter detection.
Sync Detection for H/V Sync.
DVI/HDCP/HDMI Compliant Input Ports.
Four HDMI/DVI Inputs ports.
HDMI 1.3/1.4 compliant.
MStar I Switch for fast HDMI switching.
HDCP 1.1/1.3 Copmpilant.
225MHz @ 1080P 60 Hz input with 12-bit
Deep-colour support.
Supports HDMI CEC .
Supports HDMI 1.4a 3D format input.
Support HDMI 4Kx2K input.
Single link DVI 1.0 compliant.
Robust receiver with excellent long-cable
support.
_________________________________________________
1
Trademark of Dolby laboratories
.
2
Trademark of SRS Labs. Inc.
3
Registered trademark of BBE Sound, Inc.
4
Registered trademark of QSound Labs, Inc
5
Registered trademark of Audyssey Laboratories Inc.
Optional see Order ling guide for details.
Optional see Order ling guide for details .
Optional see Order ling guide for details .
6
Registered trademark of HDMI Licensing LLC.
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LC-32/40LE361
LC-32/40LE360
LC-32/40LE362
LC-32/40LE363
MStar Advanced Color Engine- Professional
Edition (MStarACE
PRO
)
10/12-internal data processing.
High taps and fully programmable multi-
function scaling engine.
-
-
Nonlinear video scaling supports
various modes including Panorama.
-
Supports dynamic scaling for RM, VC-
1
optional
.
High-Quality DTV video processor.
-
3D motion video deinterlacer with
motion object stabilizer.
-
Edge-oriented deinterlacer with edge
and artifact smoother.
-
Automatic 3:2/ 2:2/M:N pull-down
detection and recovery.
-
3D multi-purpose noise reduction for
DTV or lousy air/ cable input.
-
MPEG artifact removal including de-
blocking and mosquito noise reduction.
-
Arbitrary frame rate conversion.
Automatic picture enhancement:
-
Includes all features in MACE-3/4
engine.
-
3D adaptive color control enabling vivid
visual reception in the true world from
most dark to most bright scenes.
most dark to most bright scenes.
-
3D adaptive sharpening control enabling
crystal clear visual reception without
distorting scene reality.
distorting scene reality.
-
Supports sRGB and xvYCC color
processing
-
Supports HDMI 1.3 deep color format.
-
Supports enhanced and seamless color
mapping for wider gamut panels.
Programmable 12-bit RGB gamma Clut.
Supports 2D to 3D conversion-
Output Interface
Single/dual link 8/10-bit LVDS output.
Supports panel resolution up to Full-HD
(1920x1080) “ 60Hz.
Supports dithering options.
Spread spectrum output frequency for EMI
suppression.
CVBS Video Encoder
Supports all NTSC/PAL TV Standard.
Stand-alone scaling engine.
Programmable HUE, Contract, Brightness.
Supports TTX/CC/WSS output
CVBS Video Outputs
Allows CVBS output from CVBS video
encoder.
Supports CVBS bypass output.
3D-like Graphics Engine.
Hardware Graphics Engine for responsive
interactive applications.
Supports point Draw and trapezoid draw.
BitBit, stretch BitBit, trapezoid BitBit,
mirror BitBit and rotate BitBit.
Supports alpha and destination alpha
compare.
Raster Operation (ROP).
Supports Porter-Duff.
VIF Demodulator
Compliant with NTSC M/N,PAL B,
G/H,I,D/K, SECAM L/L’ standards.
Digital low IF architecture.
Audio/Video dual-path processor.
Stopped-gain PGA with 25 dB tuning range
and 1dB tuning resolution.
Maximum IF gain of 37 dB.
Programmable TOP to accommodate
different tuner gain and SAW filter
insertion loss to optimize noise and
linearity performance.
insertion loss to optimize noise and
linearity performance.
Multi-standard processing with single
SAW.
Supports silicon tuner low IF output
architecture.
DVB-T/DVB-C Demodulator
Digital carrier frequency offset correction:
±500KHz.
Optimized for SFN channels with pre/pos-
cursive echoes inside/outside the guard.
Acquisition range ±857KHz includes up to
3x±1/6 MHz transmitter offset.
Meets Nordig Unified 1.0.3, D-Book
5.0,EICTA E-Book/C-Book test requirement.
ITU J.83 Annex A/C, DVB-C (EN 300 429)
compliant.
Supports DVB-C 0.7-7M Baud symbol rate.
±KHz internal carrier offset recovery range.
6.8 usecs echo cancellation at 7 Msym/s.
Supports IF, Low-IF inputs.
Ultra-fast automatic blind UHF/VHF
channel scan(constellations and symbol
rate)
rate)
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DVB-T2 Demodulator
Compliant with DVB-T2 (ETSI EN 302 755)
v1.3.1
Supports all guard intervals (1/128 to 1/49
Supports all FFT modes from 1K to 32K
Supports all long and short block code rates
(1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 2/5, 1/3)
Supports all constellations (QPSK, 16-QAM, 64-
QAM, 256-QAM)
Transmit diversity (MISO) support
Supports all scattered pilot patterns (PP1 to
PP8)
Supports rotated and no-rotated
constellations
Supports single and multiple PLPs
Accept IF, low IF inputs in 1.7, 5, 6, 7, 8MHz
channel bandwidths
All digital demodulation and timing recovery
loops for tracking frequency and clock offset
Automatic co-channel interference
suppression
Impulse-Noise suppression
Nordig Unified 2.2.2, D-Book 7.0 compliant
Connectivity
Two USB 2.0 host parts.
USB architecture designed for efficient support
of external storage devices in conjunction with
off air broadcasting.
off air broadcasting.
Built-in 10/100Mbps Ethernet PHY and MAC.
MStar proprietary I/F for Wi-Fi and Bluetooth
companion chips.
Miscellaneous
DRAM interface supporting up to two 16-bit
DDR3 @ 1,6GHz.
Supports RTC
Supports Common Interface for conditional
access support.
Bootable SPI interface with serial flash support.
Power control module with ultra low power
MCU available in standby mode.
568-ball LFBGA package.
Operationg Voltages 1.2v (core) 1.5v (DDR3),
2,5v and 3,3v (I/O and analog)
24
Table 9: Recommended operating conditions
6. 1GB DDR3 SDRAM
Hynix H5TQ1G630FA
a.
Description
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and high
bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling
edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and
falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling
edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
DVB-T2 Demodulator
Compliant with DVB-T2 (ETSI EN 302 755)
v1.3.1
Supports all guard intervals (1/128 to 1/49
Supports all FFT modes from 1K to 32K
Supports all long and short block code rates
(1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 2/5, 1/3)
Supports all constellations (QPSK, 16-QAM, 64-
QAM, 256-QAM)
Transmit diversity (MISO) support
Supports all scattered pilot patterns (PP1 to
PP8)
Supports rotated and no-rotated
constellations
Supports single and multiple PLPs
Accept IF, low IF inputs in 1.7, 5, 6, 7, 8MHz
channel bandwidths
All digital demodulation and timing recovery
loops for tracking frequency and clock offset
Automatic co-channel interference
suppression
Impulse-Noise suppression
Nordig Unified 2.2.2, D-Book 7.0 compliant
Connectivity
Two USB 2.0 host parts.
USB architecture designed for efficient support
of external storage devices in conjunction with
off air broadcasting.
off air broadcasting.
Built-in 10/100Mbps Ethernet PHY and MAC.
MStar proprietary I/F for Wi-Fi and Bluetooth
companion chips.
Miscellaneous
DRAM interface supporting up to two 16-bit
DDR3 @ 1,6GHz.
Supports RTC
Supports Common Interface for conditional
access support.
Bootable SPI interface with serial flash support.
Power control module with ultra low power
MCU available in standby mode.
568-ball LFBGA package.
Operationg Voltages 1.2v (core) 1.5v (DDR3),
2,5v and 3,3v (I/O and analog)
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LC-32/40LE360
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LC-32/40LE363
5. 1GB DDR3 SDRAM
Hynix H5TQ1G630FA
a. Description
The H5TQ1G6(8)3DFR-xxx series are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3)
Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced
to both rising and falling edges of the clock. While all addresses and control inputs are latched on the
rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced
to both rising and falling edges of the clock. While all addresses and control inputs are latched on the
rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are
sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched
to achieve very high bandwidth.
b. Features
• DQ Power & Power supply : VDD & VDDQ = 1.5V +/- 0.075V
• DQ Ground supply : VSSQ = Ground
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.
• Programmable BL=4 supported (tCCD=2CLK) for Digi-tal consumer Applications.
• Programmable ZQ calibration supported
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC) -7.8 μs at -40oC ~ 85 oC -3.9 μs at 85oC ~ 95 oC
• DQ Ground supply : VSSQ = Ground
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Programmable PASR(Partial Array Self-Refresh) for Digital consumer Applications.
• Programmable BL=4 supported (tCCD=2CLK) for Digi-tal consumer Applications.
• Programmable ZQ calibration supported
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC) -7.8 μs at -40oC ~ 85 oC -3.9 μs at 85oC ~ 95 oC
-Commercial Temperature ( 0oC ~ 85 oC) -Industrial Temperature ( -40oC ~ 85 oC)
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• On Die Thermal Sensor supported
• 8 bit pre-fetch
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• On Die Thermal Sensor supported
• 8 bit pre-fetch
Table 10: Recommended operating conditions
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