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The  Microchip  Technology  Inc.  24C32  is  a  4K  x  8  (32K  bit)  Serial  Electrically  Erasable 
PROM.  This  device  has been  developed  for  advanced,  low  power  applications  such  as 
personal communications or data acquisition. The 24C32 features an input cache for fast 
write loads with a capacity of eight 8-byte pages, or 64 bytes. It also features a fixed 4K-
bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is 
capable of both random and sequential reads up to the 32K boundary. Functional address 
lines  allow up  to  eight  24C32  devices  on  the  same  bus,  for  up  to 256K  bits  address 
space.  Advanced  CMOS  technology makes  this  device  ideal  for  low-power  non-volatile
code and data applications. The 24C32 is available in the standard 8-pin plastic DIP and 
8-pin surface mount SOIC package.

 Voltage operating range: 4.5V to 5.5V

 Peak write current 3 mA at 5.5V

 Maximum read current 150 µA at 5.5V

 Standby current 1 µA typical

 Industry standard two-wire bus protocol, I2C compatible

 Including 100 kHz and 400 kHz modes

 Self-timed write cycle (including auto-erase)

 Power on/off data protection circuitry

 Endurance: 10,000,000 Erase/Write cycles guaranteed for High Endurance Block, 

1,000,000 E/W cycles guaranteed for Standard Endurance Block

 8 byte page, or byte modes available

 1 page x 8 line input cache (64 bytes) for fast write loads

 Schmitt trigger, filtered inputs for noise suppression

 Output slope control to eliminate ground bounce

 2 ms typical write cycle time, byte or page

 Up to 8 chips may be connected to the same bus for up to 256K bits total memory

 Electrostatic discharge protection > 4000V

 Data retention > 200 years

 8-pin PDIP/SOIC packages

 Temperature ranges: Commercial (C): 0°C to +70°C, Industrial (I): -40°C to +85°C

The  MX25L512  is  a  CMOS  524,288  bit  serial  Flash  memory,  which  is  configured  as 
65,536  x  8  internally.  The  MX25L512 feature  a  serial  peripheral  interface  and  software 
protocol  allowing  operation  on  a  simple  3-wire  bus.  The  three  bus  signals are  a  clock 
input  (SCLK),  a  serial  data  input  (SI),  and  a  serial  data  output  (SO).  SPI  access  to  the 
device  is  enabled  by CS#  input. The  MX25L512  provide  sequential  read  operation  on 
whole  chip. After  program/erase  command  is  issued,  auto  program/  erase  algorithms 
which  program/  erase  and  verify  the  specified page  or  sector/block  locations  will  be 
executed.  Program  command  is  executed  on  page  (256  bytes)  basis,  and  erase
command is executes on chip or sector (4K-bytes). To provide user with ease of interface, 
a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via 
WIP bit. When the device is not in operation and CS# is high, it is put in standby mode 
and draws less than 10uA DC current. The MX25L512 utilize MXIC's proprietary memory 
cell, which reliably stores memory contents even after 100,000 program and erase cycles.

GENERAL
 Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3

 524,288 x 1 bit structure

 16 Equal Sectors with 4K byte each

 Any Sector can be erased individually

 Single Power Supply Operation

 2.7 to 3.6 volt for read, erase, and program operations

 Latch-up protected to 100mA from -1V to Vcc +1V

 Low Vcc write inhibit is from 1.5V to 2.5V

PERFORMANCE
 High Performance

 Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock 

(30pF + 1TTL Load)

 Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)

 Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) 

and 2s(max.)/chip(512Kb)

 Low Power Consumption

 Low  active  read  current:  12mA(max.)  at  85MHz,  8mA(max.)  at  66MHz  and 

4mA(max.) at 33MHz

 Low active programming current: 15mA (max.)

 Low active erase current: 15mA (max.)

 Low standby current: 10uA (max.)

 Deep power-down mode 1uA (typical)

 Minimum 100,000 erase/program cycles