DOWNLOAD Sharp LC-37GE1E (serv.man8) Service Manual ↓ Size: 174.96 KB | Pages: 24 in PDF or view online for FREE

Model
LC-37GE1E (serv.man8)
Pages
24
Size
174.96 KB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Functions of IC's
File
lc-37ge1e-sm8.pdf
Date

Sharp LC-37GE1E (serv.man8) Service Manual ▷ View online

LC-37GE1E
8 – 13
123
656I62
I
Digital (luminance) input
124
656I72
I
Digital (luminance) input
125
CLKIN2
I
Clock input [max. 81.0 MHz]
126
UVIN0
I
Digital (chrominance) input [LSB]
127
UVIN1
I
Digital (chrominance) input
128
UVIN2
I
Digital (chrominance) input
129
UVIN3
I
Digital (chrominance) input
130
VSSP8
S
Supply digital core (0 V)
131
VDDP8
S
Supply digital core (3.3 V)
132
VDD8M
S
Supply memory (1.8 V)
133
VSSD60
S
Supply digital core (0 V)
134
VSSD61
S
Supply digital core (0 V)
135
VDDD60
S
Supply digital core (1.8V)
136
VDDD61
S
Supply digital core (1.8 V)
137
UVIN4
I
Digital (chrominance) input
138
UVIN5
I
Digital (chrominance) input
139
UVIN6
I
Digital (chrominance) input
140
UVIN7
I
Digital (chrominance) input [MSB]
141
NC
-
No Connection
142
656I0/YIN0
I
Digital (luminance) input [LSB]
143
VSSP9
S
Supply digital pad (0 V)
144
VDDP9
S
Supply digital pad (3.3 V)
LC-37GE1E
8 – 14
8. IC1710: RH-IXB763WJZZ
FPGA
Pin No.
Pin Name
I/O
Pin Function
Net Name
1
EXP[8]
O
REG2 Light Control System Identify
REG2
2
EXP[9]
O
REG External Sync Identify
REG 
3
EXP[10]
O
QS Parameter
TEMP3
4
EXP[11]
O
QS Parameter
TEMP2
5
EXP[12]
O
QS Parameter
TEMP1
6
EXP[13]
O
QS Parameter
QSSET
7
EXP[14]
O
LED SLEEP
LEDSLP
8
EXP[15]
O
LED OPC
LEDOPC
9
VCCIO1 3.3V
-
Power Supply 3.3V.
3.3V
10
GND
-
Ground.
GND
11
GND
-
Ground.
GND
12
PCLK
I
Panel  Clock 74.25MHz
PCLK
13
VCCINT 3.3V
-
Power Supply 3.3V.
3.3V
14
I/O
-
GND*
open
15
I/O
-
GND*
open
16
I/O
-
GND*
open
17
OSCOUT
O
Light Control Clock Output
OSC
18
I/O
-
GND*
open
19
OFLOUT
O
Light Control PWM Output
OFL1
20
I/O
-
GND*
OFL2
21
I/O
-
GND*
open
22
(TMS)
I
Inline Program JTAG TMS/ OPEN
TMS
23
(TDI)
I
Inline Program JTAG DataIn / OPEN
TDI
24
(TCK)
I
Inline Program JTAG Clock/ OPEN
TCK
25
(TDO)
O
Inline Program JTAG DataOut / OPEN
TDO
26
I/O
-
GND*
open
27
I/O
-
GND*
open
28
I/O
-
GND*
open
29
I/O
-
GND*
open
30
I/O
-
GND*
open
31
VCCIO1 3.3V
-
Power Supply 3.3V.
3.3V
32
GND
-
Ground.
GND
33
I/O
-
GND*
open
34
EXP[16]
O
MSP<FmSdata>[amp   ]FRC Reset  Note 2)
RESET_A
35
EXP[17]
O
DTU-CVBS/ (S Terminal Y
⋅CVBS) Switching
G-ONSYNC
36
EXP[18]
O
DTV/PC/HDMI Switching
DTVPC
37
EXP[19]
O
DTV/PC/HDMI Switching
DTVHDMI
38
EXP[20]
O
E2PROM WP for HDMI
HDMI_WP
39
EXP[21]
O
Panel Flip Horizontal
LCDLR
40
EXP[22]
O
Panel Flip Vertical
LCDUD
41
EXP[23]
O
Panel 50/60Hz
FRAME
42
I/O
-
GND*
open
43
I/O
-
GND*
open
44
I/O
-
GND*
open
45
VCCIO1 3.3V
-
Power Supply 3.3V.
3.3V
46
GND
-
Ground.
GND
47
EXP[24]
O
No used.
open
48
EXP[25]
O
No used.
open
49
EXP[26]
O
CS1
CS1
50
EXP[27]
O
P-CON1
51
EXP[28]
O
BANK
BANK
52
EXP[29]
O
No used.
open
53
EXP[30]
O
No used.
open
54
EXP[31]
O
Reset trigger
open
55
I/O
-
GND*
open
56
I/O
-
GND*
open
57
I/O
-
GND*
open
58
I/O
-
GND*
open
59
VCCIO2 3.3V
-
Power Supply 3.3V.
3.3V
60
GND
-
Ground.
GND
61
I/O
-
No used.
open
62
GCLR
I
VGC_Reset_Line
RESET_N
LC-37GE1E
8 – 15
63
VCCINT 3.3V
-
3.3V
3.3V
64
SCK
I
from VGC
FPGA_SCK
65
GND
-
Ground.
GND
66
SEN
I
from VGC
FPGA_SDK
67
SDAI
I
from VGC
FPGA_SDA
68
I/O
-
GND*
open
69
SDAO
O
from VGC (GND*)
FPGA_SDAO
70
I/O
-
GND*
open
71
I/O
-
GND*
open
72
I/O
-
GND*
open
73
I/O
-
GND*
open
74
I/O
-
GND*
open
75
I/O
-
GND*
open
76
I/O
-
GND*
open
77
I/O
O
VGCwrite (Open Drain)
BOOT
78
I/O
-
GND*
open
79
GND
-
Ground.
GND
80
VCCIO2 3.3V
-
Power Supply 3.3V.
3.3V
81
I/O
I
VSYNC_OSC.
VSYNC_OSC
82
I/O
I
HSYNC_OSC.
HSYNC_OSC
83
I/O
-
GND*
open
84
I/O
-
GND*
open
85
EXP[0]
O
DTI2CSEL
DTI2CSEL
86
EXP[1]
O
DTM_RESET.
DTM_RESET
87
EXP[2]
O
DTU_ON.
DTU_ON
88
EXP[3]
O
232C ON/OFF SW
I REM-SW
89
EXP[4]
O
STB(LAMP ON)
STB
90
EXP[5]
O
S2_MUTE.
S2_MUTE
91
EXP[6]
O
ANT+5V ON.
ANT+5V ON
92
EXP[7]
O
S_MUTE.
S_MUTE
93
GND
-
Ground.
GND
94
VCCIO2 3.3V
-
Power Supply 3.3V.
3.3V
95
I/O
-
GND*
open
96
I/O
-
GND*
open
97
I/O
-
GND*
open
98
I/O
-
GND*
open
99
I/O
-
GND*
open
100
I/O
-
GND*
open
LC-37GE1E
8 – 16
9. IC1712: VHIMP1410ES-1
Step Down Converter.
10. IC1706: VHIMP1583++-1
Step Down Converter
Pin No.
Pin Name
I/O
Pin Function
1
BS
I
High-Side Gate Drive Boost input.
BS supplies the drive for the high-side n-channel MOSFET switch.
Connect a 10nF or greater capacitor from SW to BS to power the high-side switch.
2
IN
I
Power input.
IN supplies the power to the IC,as well as the step-down converter switches.
Drive IN with a 4.75V to 15V power source.
Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC.
See input Capacitor.
3
SW
O
Power Switching Output. 
SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load.
Note that a capacitor is required from SW to BS to power the high-side switch.
4
GND
-
Ground.
5
FB
I
Feedback input.
FB senses the output voltage to regulate that voltage.
Drive FB with a resistive voltage divider from the output voltage. 
The feedback threshold is 1.22V.
See Setting the Output Voltage.
6
COMP
-
Compensation Node.
COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation control loop.
See Compensation.
7
EN
I
Enable input.
EN is a digital input that turns the regulator on or off.
Drive EN high to turn on the regulator,drive it low to turn it off.
For automatic startup,leave EN unconnected.
8
N/C
-
No Connect.
Pin No.
Pin Name
I/O
Pin Function
1
BS
I
High-Side Gate Drive Boost lnput.
BS supplies the drive for the high-side n-channel MOSFET Switch.
Connect a 4.7nF or greater capacitor from SW to BS to power the high side switch.         
2
IN
I
Power input.
IN supplies the power to the IC, as well as the step-down converter switches.
Drive IN with a 4.75V to 23V power  source.
Bypass IN to GND with a suitably  large capacitor to eliminate noise on the input to the IC.
See Input Capacitor.        
3
SW
O
Power Switching Output.
SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load.
Note that a capacitor is required from SW to BS to power the high-side switch.        
4
GND
-
Ground. (Note: Connect the exposed pad on backside to Pin4).         
5
FB
I
Feedback input.
FB senses the output voltage to regulate that voltage.
Drive FB with a resistive voltage divider from the output voltage.
The feedback threshold is 1.222V.
See  Setting the Output Voltage.     
6
COMP
I
Compensation Node.
COMP is used to compensate the regulation control loop.
Connect a series RC network from COMP to GND to compensate the regulation control loop.
In same cases,  an additional capacitor from COMP to GND is required.
See Compensation.        
7
EN
I
Enable input 
EN is a digital input that turns the regulator on or off.
Drive EN high to turn on the regulator, drive it low to tum it off .
For automatic startup, leave EN unconnected.        
8
SS
I
Soft Start Control input.
SS controls the soft start period.
Connect a capacitor from SS to GND to set the soft-start period.
A 0.1
μF capacitor sets the soft-start period to l0ms
To disable the soft-start featur CIeave SS unconnected.       
Page of 24
Display

Click on the first or last page to see other LC-37GE1E (serv.man8) service manuals if exist.