DOWNLOAD Sharp LC-32SH130K (serv.man8) Service Manual ↓ Size: 7.46 MB | Pages: 45 in PDF or view online for FREE

Model
LC-32SH130K (serv.man8)
Pages
45
Size
7.46 MB
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PDF
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Service Manual
Brand
Device
TV / LCD / Circuit Descriptions
File
lc-32sh130k-sm8.pdf
Date

Sharp LC-32SH130K (serv.man8) Service Manual ▷ View online

53
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LC-32SH340E
15. NAND FLASH MEMORY – NAND512XXA2C (U162)
15.1.
General Description
The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single 
level cell (SLC) NAND technology. It is referred to as the small page family.
The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with 
either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words 
(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/output signals on a multiplexed x8 or x16 
input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities 
without changing the footprint.
To extend the lifetime of NAND flash devices it is strongly recommended to implement an error 
correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles 
for each block. A write protect pin is available to give a hardware protection against program and erase 
operations.
15.2.
Features
High density NAND flash memories
512-Mbit memory array
Cost effective solutions for mass storage applications
NAND interface
x8 or x16 bus width
Multiplexed address/ data
Supply voltage: 1.8 V, 3 V
Page size
x8 device: (512 + 16 spare) bytes
x16 device: (256 + 8 spare) words
Block size
x8 device: (16K + 512 spare) bytes
x16 device: (8K + 256 spare) words
Page read/program
Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
Page program time: 200 μs (typ)
Copy back program mode
Fast block erase: 2 ms (typ)
Status register
14.
14.1
14.2
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Electronic signature
Chip Enable ‘don’t care’
Security features
o OTP area
Serial number (unique ID) option
Hardware data protection
o Program/erase locked during power transitions
Data integrity
o 100,000 program/erase cycles (with ECC)
o 10 years data retention
RoHS compliant packages
Development tools
o Error correction code models
o Bad blocks management and wear leveling algorithms
15.3.
Pinning
14.3
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16. USB2.0 to Fast Ethernet – ASIX AX88X72A (U171)
16.1.
General Description
The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high 
performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-
play Fast Ethernet network connection capability for desktops, notebook PC’s, Ultra-Mobile PC’s, docking 
stations, game consoles, digital-home appliances, and any embedded system using a standard USB port.
The AX88772A/AX88172A features a USB interface to communicate with a USB Host Controller and is 
compliant with USB specification V1.1 and V2.0. The AX88772A/AX88172A implements 10/100Mbps 
Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards with 24KB of embedded SRAM for 
packet buffering. The AX88772A/AX88172A integrates an on-chip 10/100Mbps Ethernet PHY to simplify 
system design.
The AX88172A provides an optional External Media Interface (EMI) for external PHY or external MAC for 
different application purposes. The EMI can be a media-independent interface (MII) for implementing 
100BASE-FX Ethernet or HomePNA functions. The EMI can also be a Reverse-MII or Reverse Reduced-MII 
(Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC MII or RMII interface. 
In addition, the EMI can be configured to Dual-PHY mode allowing AX88172A to act as an Ethernet PHY or 
USB 2.0 PHY for external MAC device that needs Ethernet and USB interfaces in their system applications. 
The optional serial interface such as I2C, SPI, and UART are provided as a control channel from the USB 
Host Controller to communicate with the external MCU chip.
16.2.
Features
Single chip USB 2.0 to 10/100M Fast Ethernet controller – AX88772A
USB Device Interface
Integrates on-chip USB 2.0 transceiver and SIE compliant to USB Spec 1.1 and 2.0
Supports USB Full and High Speed modes with Bus-Power or Self-Power capability
Supports 4 or 6 programmable endpoints on USB interface
High performance packet transfer rate over USB bus using proprietary burst transfer 
mechanism 
Supports USB to Ethernet bridging or vice versa in hardware
Fast Ethernet Controller
Integrates 10/100Mbps Fast Ethernet MAC/PHY
IEEE 802.3 10BASE-T/100BASE-TX compatible
Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX)
Embedded 16KB SRAM for RX packet buffering and 8KB SRAM for TX packet buffering
Supports both Full-duplex with flow control and
Half-duplex with backpressure operation
Supports 2 VLAN ID filtering, received VLAN Tag (4 bytes) can be stripped off or preserved 
MAC/PHY loop-back diagnostic capability
Support Wake-on-LAN Function
15.
15.2
15.1
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Supports Suspend Mode and Remote Wakeup via Link-up, Magic packet, MS wakeup frame 
and external pin
Optional PHY power down during Suspend Mode
Versatile External Media Interface
Optional MII interface in MAC mode allows AX88172A to work with external 100BASE-FX 
Ethernet PHY or HomePNA PHY
Optional Reverse-MII or Reverse-RMII interface in PHY mode allows AX88172A to work with 
external HomePlug PHY or glueless MAC-to-MAC connections
Optional Reverse-MII interface in Dual-PHY mode allows AX88172A to act as an Ethernet 
PHY or USB 2.0 PHY for external MAC device that needs Ethernet and USB in system 
application
Supports 256/512 bytes (93c56/93c66) of serial EEPROM (for storing USB Descriptors)
Supports automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration 
from EEPROM after power-on initialization
Provides optional serial interface, I2C, SPI and UART
Integrates on-chip voltage regulator and only requires a single 3.3V power supply
12MHz and 25Mhz clock input from either crystal or oscillator source
Integrates on-chip power-on reset circuit
16.3.
Block Diagram
16.4.
Pinning
17. LM1117(U175, U180, U181)
17.1.
General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It 
has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an 
adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In 
addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers 
current limiting and thermal shutdown. Its circuit includes a zener trimmed band-gap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, 
TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to 
improve the transient response and stability.
17.2.
Features
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0°C to 125°C
LM1117I -40°C to 125°C
15.4
15.3
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