Sharp LC-32LD145E Service Manual ▷ View online
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6. DDR3 SDRAM 1Gb G-die
6.1 Description:
The 1Gb DDR3 SDRAM G-die is organized as a 8Mbit x 16 I/Os x 8banks device. This
synchronous device achieves high speed double-data-rate transfer rates of up to
2133Mb/sec/pin(DDR3-2133)for general applications. The chip is designed to comply with
the following key DDR3 SDRAM features such as posted CAS, Programmable CWL,
Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All
of the control and address inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in
a source synchronous fashion. The address bus is used to convey row, column, and bank
address information in a RAS/CAS multiplexing style. The DDR3 device operates with a
single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device
is available in 96ball FBGA(x16).
6.2 Features
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin,
800MHz fCK for 1600Mb/sec/pin, 933 MHz fCK for 1866Mb/sec/pin,
1066 MHz fCK for 2133Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5, 6, 7, 8, 9, 10, 11, 12,
13, 14
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 6 (DDR3-1066), 7
(DDR3-1333), 8 (DDR3-1600), 9 (DDR3-1866), 10 (DDR3-2133)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 1Gb DDR3 SDRAM G-die is organized as a 8Mbit x 16 I/Os x 8banks device. This
synchronous device achieves high speed double-data-rate transfer rates of up to
2133Mb/sec/pin(DDR3-2133)for general applications. The chip is designed to comply with
the following key DDR3 SDRAM features such as posted CAS, Programmable CWL,
Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All
of the control and address inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in
a source synchronous fashion. The address bus is used to convey row, column, and bank
address information in a RAS/CAS multiplexing style. The DDR3 device operates with a
single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device
is available in 96ball FBGA(x16).
6.2 Features
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin,
800MHz fCK for 1600Mb/sec/pin, 933 MHz fCK for 1866Mb/sec/pin,
1066 MHz fCK for 2133Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5, 6, 7, 8, 9, 10, 11, 12,
13, 14
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 6 (DDR3-1066), 7
(DDR3-1333), 8 (DDR3-1600), 9 (DDR3-1866), 10 (DDR3-2133)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
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x16 Package Pinout (Top view) : 96ball FBGA Package
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7. SCALER AND LVDS SOCKETS
7.1. LVDS sockets Block Diagram
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7.2. Panel Supply Switch Circuit
This switch is used to open and close panel supply of TCON. It is controlled by port of main
ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel supplys
are connected to this circuit. All of them are optional according to panels.
ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel supplys
are connected to this circuit. All of them are optional according to panels.
8. SPI FLASH MEMORY
8.1
EN25Q64 64 Megabit Serial Flash Memory with 4Kbyte Uniform
Sector
8.1.1 General Description
The EN25Q64 is a 64 Megabit (8192K-byte) Serial Flash memory, with advanced write
protection mechanisms. The EN25Q64 supports the standard Serial Peripheral Interface
(SPI), and a high performance Dual output as well as Quad I/O using SPI pins: Serial
Clock, Chip Select, Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock
frequencies of up to 50MHz are supported allowing equivalent clock rates of 100MHz for
Dual Output and 200MHz for Quad Output when using the Dual/Quad Output Fast Read
instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page
Program instruction. The EN25Q64 is designed to allow either single Sector/Block at a time
or full chip erase operation. The EN25Q64 can be configured to protect part of the memory
as the software protected mode. The device can sustain a minimum of 100K program/erase
cycles on each sector or block.
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