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A/B MUX

RINA/YINA

GND
VCC
RINB/YINB

GINA/UINA

GINB/UINB

BINA/VINA

BINB/VINB

BOUT
GOUT
VCCO
ROUT
GNDO
DISABLE
SYNC IN

—

I

—
—

I

I

I

I

I

O
O

—

O

—

I
I

Logic input pin to select between Bank <A> and Bank <B> video inputs.
This pin is internally pulled high.
Unfiltered analog R- or Y-channel input for Bank <A>, Sync must be provided at SYNC
IN pin.
Analog ground.
Analog 5V supply.
Unfiltered analog R or Y-channel input for Bank <B>, Sync must be provided at SYNC
IN pin.
Unfiltered analog G or U-channel input for Bank <A>, Sync must be provided at SYNC
IN pin.
Unfiltered analog G or U-channel input for Bank <B>, Sync must be provided at SYNC
IN pin.
Unfiltered analog B or V-channel input for Bank <A>, Sync must be provided at SYNC
IN pin.
Unfiltered analog B or V-channel input for Bank <B>, Sync must be provided at SYNC
IN pin.
Analog B or V-channel output.
Analog G or U-channel output.
5V power supply for output buffers.
Analog R or Y-channel output.
Analog ground.
Disable/Enable pin. Turns the chip off when logic high. Internally pulled low.
Input for an external H-sync logic signal for filter channels. CMOS level input. Active
High.

Ë

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* RH-iX3473CEZZ is 6.7MHz at Cut-off frequency.
* RH-iX3474CEZZ is 30MHz at Cut-off frequency.

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DVI-D  

TMDS  

Rx Core 

Content 

Protection 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DVI-D  

SiI  

151 

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QE[23-0]

86-79,

Out

Output Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock in mode and to the first
24-bit pixel data for 2-pixels/clock mode. Output dat synchronized with output data clock (ODCK).
See section 21 on page 38 for the output data mapping of these pins.

QO[23:0]

158,

Out

Output Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. Dur-
ing 1-pixel/clock mode, these outputs are forced LOW.
Output data is synchronized with output data clock (ODCK). See section 21 on page 38 for the
output data mapping of these pins.

ODCK

93

Out

Output Data Clock.

ODCK_D

102

Out

Output Data Clock Delayed. Controlled by register VSD1[3:2] on page 82.

DE

95

Out

Output Data Enable. This signal qualifies the active data area. A HIGH level signifies valid display
time. A LOW level signifies a valid blanking time.

HSYNC

97

Out

Horizontal Sync control signal.

VSYNC

96

Out

Vertical Sync control signal.

CTL1 / IVS

89

Out

Control signals from the transmitter and internal XCLK or input HSYNC, input VSYNC, input DE

and input CLOCK (ICLK). RMDT[7] determines the function of these pins. See section 15 for
RMDT[7] control information. CTL 3 is also used as a strapping option to enable/disable the 5x
clock multiplier, high=bypass and low=enable 5x.

TX_0-

182

Analog

LVDS output data pairs.

TX_0+

181

TX_1-

180

TX_1+

179

TX_2-

176

TX_2+

175

TX_3-

172

TX_3+

171

TX_CK-

174

Analog

LVDS output clock pair.

TX_CK+

173

SCL

165

I/O

I

2

C Clock. This pin is open drain.

SDA

166

I/O

I

2

C Data. This pin is open drain.

MSTATE

164

Out

I

2

C Bus Master. The pin goes HIGH upon RESET LOW and goes LOW after the SiI861 has

finished mastering the I

2

C bus.

KEY_SCL

150

I/O

Cipher Key I

2

C Clock. This pin is open drain.

KEY_SDA

149

I/O

Cipher Key I

2

C Data. This pin is open drain.

DDC_SCL

152

I/O

DDC/Authentication I

2

C Clock. This pin is open drain.

DDC_SDA

151

I/O

DDC/Authentication I

2

C Data. This pin is open drain.

PD#

4

In

Power Down (active LOW). A HIGH level (3.3V) indicates normal operation and a LOW level
indicates power down mode. Register FDIV[7] determines the power down mode entered: 1 =
Power down, 0 = Pull down
The I

2

C register values are retained in Power Down mode but the I

2

C interface is disabled.

ON_OFF /

7

Out

On_Off / Loss of Sync. In non-DVI mode, a HIGH level indicates that the link from the transmitter
to the SiI861 is active. A LOW level indicates that the link from the transmitter to the SiI861 is not
active.

74-73,
33-28,
23-16

145-139,
132-125
122-117,
99-98

CTL2 / IHS

90

Out

CTL3 / IDE

91

Out

TPCLK

105

Out

L_SYNC#

In DVI mode, a HIGH level indicates that the link from the transmitter to the SiI861 is active. A
LOW level indicates a “Loss of Sync” condition between the transmitter and the SiI861.
Please refer to the Section 8. PD does not affect this output when operating in pull-down mode

STDBY/

5

Out

Standby. In non-DVI mode, a HIGH level indicates a standby condition. A LOW level indicates a
normal active condition.
In DVI mode, this pin is PWM0.
Please refer to the Section 8. PD does not affect this output when operating in pull-down mode

SUSPD /

6

Out

Suspend / Out of Range. In non-DVI mode, a HIGH level indicates a suspend condition. A LOW

level indicates a normal active condition.
In DVI mode, a HIGH level indicates an “Out of Range” condition. A LOW level indicates normal
operation.
Please refer to Section 7. PD does not affect this output.

PWM0

107

Out

Pulse Width Modulation. These pins can be used as the pulse width modulation signal to control
the backlight brightness or volume.
Please refer to the Section 13 for more information. PD# does not affect this output when in pull-
down mode

BUT0+

108

In

These pins are used to monitor pushbuttons, which can directly control the PWM0 and PWM1

outputs. BUT0+/- are used for PWM0 control, and BUT1+/- are used for PWM1 control. These
pins have internal 100K pull-down resistors.

XCLK

161

In

External clock input. See Section 6 External Clock Rate and Input Frame Rate

XTAL1

154

In

External crystal input to the inverting oscillator amplifier or clock oscillator input.
This sets the output clock frequency to the panel, which will equal this frequency or be 5 times this
frequency if the clock multiplier is used. This pin is 5V tolerant.
See Section 6 External Clock Rate and Input Frame Rate.

XTAL2

155

Out

Output from inverting oscillator amplifier when using on-chip crystal oscillator.
No-connect when using external clock.

RESET#

3

In R

eset (active LOW). When this pin is pulled LOW, the SiI861 will enter a reset state. When RESET
goes HIGH, the SiI861 begins loading the internal I2C registers automatically from the external
configuration EEPROM.

RX0+

196

Analog

TMDS TM Low Voltage Differential Signal input data pairs.

RX0-

197

Analog

Maximum input pixel clock on TMDS input is 112 MHz.

RX1+

191

Analog

RX1-

192

Analog

RX2+

186

Analog

RX2-

187

Analog

RXC+

199

Analog

TMDS TM Low Voltage Differential Signal input clock pairs.

RXC-

200

Analog

X_RES

202

Analog

Impedance Matching Control. Resistor value should be ten times the characteristic single-ended
impedance of the cable. In the common case of 50  transmission line, an external 400  resistor
must be connected between AVCC and this pin.

TMDS_SEL

112

In

Selects PanelLink or Parallel as input source. Default active high: High = PanelLink, Low = Paral-
lel. This pin has an internal 100K pull-up resistor. Polarity control can be changed in register
ADD1, see page 94 for more detail.

PD[23-0]

37-60

In

Corresponds to 24-bit pixel data for 1-pixel/clock input mode. These pins have internal 100K pull-

down resistors.

PCLK

64

In

Input data clock for parallel input. This pin has an internal 100K pull-down resistor.

PDE

61

In

Input Data Enable for parallel input. This signal qualifies the active data area. A HIGH level signi-
fies valid display time. A LOW level signifies a valid blanking time. This pin has an internal 100K
pull-down resistor.

PHS

62

In

Horizontal Sync control signal input on parallel input.

PVS

63

In

Vertical Sync control signal input on parallel input.
These pins have internal 100K pull-down resistors.

ADE

70

Out

An external DE signal is generated based on the parallel input IN_HSYNC and IN_VSYNC pins. If
using an external component that does not generate DE, such as a TV decoder, this signal should
be connected externally to IN_DE. The timing of this signal is controlled by the “DE Generation”
registers explained on page 94.

TSTMD

8

In

For TEST purposes only. Should be tied LOW.

TSTEN

9

In

For TEST purposes only. Should be tied LOW.

DVCC

2,11,27,

Power

Digital Core VCC, must be set to 2.5V.

75,87,
104,113,
137,
147,163,
208

GND

1,10,26,

Ground

Digital GND.

76,88,
103,114,
138,
148,153,

PWM0

O_RNG

PWM1

106

BUT0-

109

BUT1+

110

BUT1-

111

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156,
160,162,
207

OVCC

12,24,

Power

Output Buffers VCC, must be set to 3.3V.

78,92,
123,135,
159

OGND

13,25,

Ground

Output Buffer GND.

65,69,
77,94,
101,124,
136,
157

AVDD

170,

Power

Analog VCC, must be set to 3.3V.

178,
194

AVCC

188,

Power

Analog VCC, must be set to 3.3V.

190,
201

AGND

169,

Ground

Analog GND.

177,
185,
189,
193,
195,
198

PVCC

168,

Power

PLL Analog VCC, must be set to 3.3V.

183,
203

PGND

167,

Ground

PLL Analog GND.

184,
204

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