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         2008-03-14 

LC-26SB25E/S/RU, LC-32SB25E/S/RU, LC-42SB55E/S/RU 

 61 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

2.2.1 Pin Connections and short description 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

LC-26SB25E/S/RU, LC-32SB25E/S/RU, LC-42SB55E/S/RU 

62  

  

N° 

1 

OUT 

Regulator output 

2 

SYNCH 

Master/Slave Synchronization. When it is left floating, a signal with a phase shift of half a period respect to the power turn 
on is present at the pin. When connected to an external signal at a frequency higher than the internal one, then the 
device is synchronized by the external signal, with zero phase shift. 
Connecting together the SYNC pin of two devices, the one with higher frequency works as master and the other one as 
slave; so the two power turn on have a phase shift of half a period. 

3 

INH 

A logical signal (active high) disable the device. With INH higher than 1.9V the device is OFF and with INH lower than 
0.6V the device is ON. 

4 

COMP 

Error Amplifier output to be used for loop frequency compensation 

5 

FB 

Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.6V. To have higher 
regulated voltages an external resistor divider is required from Vout to FB pin. 

6 

F

SW

The switching frequency can be increased connecting an external resistor from FSW pin and ground. If this pin is left 
floating the deice works at its free-running frequency of 250KHz. 

7 

GND 

Ground 

8 

V

CC

Unregulated DC input voltage 

 

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

 

 

 

 

Data Signals ×16 Organization

 

G8 

DQ0 I/O 

SSTL 

G2 

DQ1 I/O 

SSTL 

H7 

DQ2 I/O 

SSTL 

H3  

DQ3 I/O 

SSTL 

H1 DQ4 

I/O 

SSTL 

H9 DQ5 

I/O 

SSTL 

F1 DQ6 

I/O 

SSTL 

F9 DQ7 

I/O 

SSTL 

C8 DQ8 

I/O 

SSTL 

C2 DQ9 

I/O 

SSTL 

D7 DQ10 

I/O 

SSTL 

D3 DQ11 

I/O 

SSTL 

D1 DQ12 

I/O 

SSTL 

D9 DQ13 

I/O 

SSTL 

B1 DQ14 

I/O 

SSTL 

B9 DQ15 

I/O 

SSTL 

Data Signal 15:0 
 

Data Strobe ×16 Organization

 

B7 UDQS 

I/O SSTL 

A8 

UDQS 

I/O SSTL 

Data Strobe Upper Byte 

F7 

LDQS 

I/O SSTL 

E8 

LDQS 

I/O SSTL 

Data Strobe Lower Byte 

Data Mask ×16 Organization

 

         2008-03-14 

LC-26SB25E/S/RU, LC-32SB25E/S/RU, LC-42SB55E/S/RU 

 63 

B3 UDM 

I SSTL 

F3 

LDM 

I SSTL 

Data Mask Upper/Lower Byte 

Power Supplies ×16 Organization

 

J2 

REF

 

AI 

— 

I/O Reference Voltage 

E9, G1, G3, G7, G9 

DDQ

 PWR  — 

I/O Driver Power Supply 

J1 

DDL

 PWR  — 

Power Supply 

E1, J9, M9, R1 

DD

 

PWR — 

Power Supply 

E7, F2, F8, H2, H8 

SSQ

 

PWR — 

I/O Driver Power Supply 

J7 

SSDL

 

PWR — 

Power Supply 

A3, 3,J3,N1,P9 

SS

 

PWR — 

Power Supply 

Not Connected ×16 Organization

 

A2, E2, L1, R3, R7, R8 

NC 

NC 

— Not 

Connected 

Other Pins ×16 Organization

 

K9 ODT 

I 

SSTL 

On-Die Termination Control 

 

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

LC-26SB25E/S/RU, LC-32SB25E/S/RU, LC-42SB55E/S/RU 

64  

 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 

 

 

VSSD(HW) 

1 

negative digital supply voltage and handle wafer connection 

IN1P 

2 

positive audio input for channel 1 

IN1N 

3 

negative audio input for channel 1 

DIAG 

4 

diagnostic output; open-drain 

ENGAGE 

5 

engage input to switch between Mute mode and Operating mode 

POWERUP 

6 

power-up input to switch between Sleep mode and Mute mode 

CGND 

7 

control ground; reference for POWERUP, ENGAGE and DIAG 

VDDA 

8 

positive analog supply voltage 

VSSA 

9 

negative analog supply voltage 

OSCREF 

10 

input internal oscillator setting (only master setting) 

HVPREF 

11 

decoupling of internal half supply voltage reference 

INREF 

12 

decoupling for input reference voltage 

TEST 

13 

test signal input; for testing purpose only 

IN2N 

14 

negative audio input for channel 2 

IN2P 

15 

positive audio input for channel 2 

VSSD(HW) 

16 

negative digital supply voltage and handle wafer connection 

VSSD(HW) 

17 

negative digital supply voltage and handle wafer connection 

DREF 

18 

decoupling of internal (reference) 5 V regulator for logic supply 

HVP2 

19 

half supply output voltage 2 for charging single-ended capacitor for channel 2  

VDDP2 

20 

positive power supply voltage for channel 2 

BOOT2 

21 

bootstrap high-side driver channel 2 

OUT2 

22 

Pulse Width Modulated (PWM) output channel 2 

VSSP2 

23 

negative power supply voltage for channel 2 

STAB2 

24 

decoupling of internal 11 V regulator for channel 2 drivers 

STAB1 

25 

decoupling of internal 11 V regulator for channel 1 drivers 

VSSP1 

26 

negative power supply voltage for channel 1 

OUT1 

27 

PWM output channel 1 

BOOT1 

28 

bootstrap capacitor for channel 1 

VDDP1 

29 

positive power supply voltage for channel 1 

HVP1 

30 

half supply output voltage 1 for charging single-ended capacitor for channel 1 

OSCIO 

31 

oscillator input in slave configuration or oscillator output in master configuration 

VSSD(HW) 

32 

negative digital supply voltage and handle wafer connection 

 

 

2.7.1 Pin Connections and short description 
 
 
 
 
 
 
 

 

 

 
 

1OUT
1IN-
1IN+
V

CC-

VCC+
2OUT
2IN-
2IN+