DOWNLOAD Sharp LC-22LE22E Service Manual ↓ Size: 7.6 MB | Pages: 121 in PDF or view online for FREE

Reset  circuit  using  for  initiliazing  main Mstar IC.  Reset  condition  is  high  and  nomal 
working condition is low for RESET pin.

It is used for CI module supply, when Module is inserted (it means CI detect is low) This 
circuit is opened or closed by CI_POWER_CTRL port of main uController

This  demodulator  is  optionall  for  support  T2  reception. The  Sony  CXD2820R  is  a 
combined  DVB-T2,  DVB-T  and  DVB-C  demodulator  that conforms  to the ETSI  EN  302-
755 (second generation Terrestrial) ETSI EN 300-744 (Terrestrial) and ETSI EN 300-429 
(Cable) standards.

 Single, 41MHz crystal (can be shared with CXD2813Ranalogue demod IC)

 High performance differential signal ADC

 RF power level monitor ADC

 Low IF and high IF (36MHz) mode input

 Fast 400kHz I2C compatible bus interface

 Quiet I2C interface for dedicated tuner control

 Automatic IF AGC and optional programmable

 RF AGC/GPIO functions

 Configurable parallel and serial MPEG-2 TS outputs with smoothing buffer

 3.3V, 2.5V, 1.2V supplies

 Temperature range -20°C to +85°C

 Supplied with full reference design, including software driver, PCB 

schematic/layouts, GUI and documentation

 3.3V for VDD and 2.5V for VDDQ power supply

 All inputs and outputs are compatible with SSTL_2 interface

 JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch

 Fully differential clock inputs (CK, /CK) operation

 Double data rate interface

 Source synchronous - data transaction aligned to bidirectional data strobe (DQS)

 x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O

 Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers 

when write (centered DQ)

 Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the 

data strobe

 All addresses and control inputs except Data, Data strobes and Data masks 

latched on the rising edges of the clock

 Write mask byte controls by LDM and UDM

 Programmable /CAS latency 3 / 4 supported

 Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode

 Internal 4 bank operations with single pulsed /RAS

 tRAS Lock-Out function supported

 Auto refresh and self refresh supported

 4096 refresh cycles / 32ms

 Full, Half and Matched Impedance(Weak) strength driver option controlled by 

EMRS