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Supports dithering options to 6/8-bit output

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Spread spectrum output for EMI suppression

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Supports all NTSC/PAL TV Standard

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Stand-alone scaling engine

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Programmable Hue, Contract, Brightness

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Supports TTX/CC/WSS output

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Allows CVBS output of all source inputs

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Hardware Graphics Engine for responsive

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Interactive applications

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Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid draw

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BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt

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Raster Operation (ROP)

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Support Porter-Duff

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Compliant with NTSC M/N, PAL B, G/H, I, D/K,

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SECAM L/L' standards

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Audio/Video dual-path processor

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Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution

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Maximum IF gain of 37 dB

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Programmable TOP to accommodate different tuner gain and SAW filter insertion 
loss to

           optimize noise and linearity performance

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Multi-standard processing with single SAW

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Supports silicon tuner low IF output  architecture

 '9%-T Demodulator

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Digital carrier frequency offset correction: ±500KHz

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Optimised for SFN channels with pre/post-cursive echoes inside/outside the guard

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Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset

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Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test requirement

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±400kHz internal carrier offset recovery range

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6.8 usecs echo cancellation at 7 Msym/s

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Supports IF, low-IF, zero-IF inputs

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Ultra-fast automatic blind UHF/VHF channel scan (constellations and symbol rate)

 &Rnnectivity

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Two USB 2.0 host ports

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USB architecture designed for efficient support of external storage devices in 
conjunction with

           off air broadcasting

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DRAM interface supporting one 16-bit DDR2 @1066MHz

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Supports PVR

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Supports Common Interface for conditional access support

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Bootable SPI interface with serial flash support

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Parallel interface for external NAND flash support

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Power control module with ultra low power MCU available in standby mode

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380-ball LFBGA package

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Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and analog)

Reset circuit using for initiliazing main Mstar IC. Reset condition is high and nomal 
working condition is low for RESET pin.

CI Interface Power Switch:
It is used for CI module supply, when Module is inserted (it means CI detect is low) This 
circuit is opened or closed by CI_POWER_CTRL port of main uController

Main Concept IC has integrated 2 USB 2.0 interface. One of them is used for ethernet 
function, the other one is used for USB connectivity for last user. Last user can play video, 
picture and  audio files. Also digital channels can be record to externall storage device by 
this interface. All SW files can be updated with interface. 

USB circuit has 3 main parts

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Integrated USB 2.0 Host interface of D3K (U5)

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Protection IC (U145)

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Over Curent Protection IC (U8)

Description:
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8 
banks device. This synchronous device achieves high speed double-data-rate transfer 
rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed 
to comply with the following key DDR2 SDRAM fea-tures such as posted CAS with 
additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance 
adjustment and On Die Termination. All of the control and address inputs are 
synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at 
the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized 
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The 
address bus is used to convey row, column, and bank address information in a RAS/CAS 
multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing. The 1Gb 
DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. 
The 1Gb DDR2 device is available in 60ball FBGA(x8) and 84ball FBGA(x16).

• JEDEC standard VDD = 1.8V ± 0.1V Power Supply 
• VDDQ = 1.8V ± 0.1V 
• 533MHz fCK for 1066Mb/sec/pin 
• 8 Banks 
• Posted CAS 
• Programmable CAS Latency: 4, 5, 6, 7 
• Programmable Additive Latency: 3, 4, 5. 6 
• Write Latency(WL) = Read Latency(RL) -1 
• Burst Length: 4 , 8(Interleave/nibble sequential) 
• Programmable Sequential / Interleave Burst Mode 
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) 
• Off-Chip Driver(OCD) Impedance Adjustment 
• On Die Termination 
• Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High 
Temperature Self-Refresh rate enable 
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 
°C 
• All of products are Lead-free, Halogen-free, and RoHS compliant