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LC-19D1E/S-BK/WH

5 – 21

28-32, 35-42 A [0 : 12]

I

Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO 
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the 
respective bank.
A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to 
one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
The address inputs also provide the op-code during a MODE REGISTER SET command.
BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS 
or EMRS).

2, 4, 5, 7, 8, 
10, 11, 13, 
54, 56, 57, 
59, 60, 62, 
63, 65

DQ

I/O

Data Input/Output : Data bus.

16,51

LDQS,(U)DQS

I/O

Data Strobe : Output with read data, input with write data.
Edge-aligned with read data,centered in write data.
Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on 
DQ8~DQ15

14, 17, 19, 
25, 43, 50, 
53

NC

-

No Connect : No internal electrical connection is present.

3, 9, 15, 55, 
61

VDDQ

-

DQ Power Supply : +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

6, 12, 52, 
58, 64

VSSQ

-

DQ Ground.

1, 18, 33

VDD

-

Power Supply : +2.5V 

± 0.2V. (+2.6V ± 0.1V for DDR400)

34, 48, 66

VSS

-

Ground.

49

VREF

SSTL_2 reference voltage.

LC-19D1E/S-BK/WH

5 – 22

16Mbit Flash Memory

 64Kbit E2PROM

1-9,16-25,48

A0-A19

I

Address Inputs

29,31,33,35,38,40,42,44

DQ0-DQ7

I/O

Data Inputs/Outputs

30,32,34,36,39,41,43

DQ8-DQ14

I/O

Data Inputs/Outputs

45

DQ15A?1

I/O

Data Input/Output or Address Input

26

E

I

Chip Enable

28

G

I

Output Enable

11

W

I

Write Enable

12

RP

I

Reset/Block Temporary Unprotect

15

RB

O

Ready/Busy Output

47

BYTE

I

Byte/Word Organization Select

37

VCC

-

Supply Voltage

27,46

VSS

-

Ground

10,13,14

NC

-

Not Connected Internally

1

A0

I

A0 signal

2

A1

I

A1 signal

3

A2

I

A2 signal

4

GND

 

-

Ground

5

SDA

I/O

Serial data

6

SCL

I

Serial clock

7

WP

I

Write Protect

8

VCC

 -

Power supply

LC-19D1E/S-BK/WH

5 – 23

Bus Tranceiver

1

DIR

I

Directory.

2

A1

I/O

A-Bus. Output/Input Terminal A1.

3

A2

I/O

A-Bus. Output/Input Terminal A2.

4

A3

I/O

A-Bus. Output/Input Terminal A3.

5

A4

I/O

A-Bus. Output/Input Terminal A4.

6

A5

I/O

A-Bus. Output/Input Terminal A5.

7

A6

I/O

A-Bus. Output/Input Terminal A6.

8

A7

I/O

A-Bus. Output/Input Terminal A7.

9

A8

I/O

A-Bus. Output/Input Terminal A8.

10

GND

-

Ground                                                   

11

B8

I/O

B-Bus Input/Output Terminal B8.

12

B7

I/O

B-Bus Input/Output Terminal B7.

13

B6

I/O

B-Bus Input/Output Terminal B6.

14

B5

I/O

B-Bus Input/Output Terminal B5

15

B4

I/O

B-Bus Input/Output Terminal B4

16

B3

I/O

B-Bus Input/Output Terminal B3

17

B2

I/O

B-Bus Input/Output Terminal B2

18

B1

I/O

B-Bus Input/Output Terminal B1

19

OE

I

Output enable.

20

VCC

-

Power Source.

LC-19D1E/S-BK/WH

5 – 24

Quad Bus Buffer

1

1OE

I

Output Enable terminal 1

2

1Y1

O

Output terminal 1Y1

3

1Y2

O

Output terminal 1Y2

4

GND

 -

Ground

5

1Y3

O

Output terminal 1Y3

6

1Y4

O

Output terminal 1Y4

7

VCC

 -

Power supply

8

2Y1

O

Output terminal 2Y1

9

2Y2

O

Output terminal 2Y2

10

GND

 -

Ground

11

2Y3

O

Output terminal 2Y3

12

2Y4

O

Output terminal 2Y4