Sharp LC-19D1EWH (serv.man6) Service Manual ▷ View online
LC-19D1E/S-BK/WH
5 – 17
65
FMIADDR14
O
Adress data 14 (for flash )
FMIADDBE14
66
FMIADDR13
O
Adress data 13 (for flash )
FMIADDBE13
69
FMIADDR12
O
Adress data 12 (for flash )
FMIADDBE12
70
FMIADDR11
O
Adress data 11 (for flash )
FMIADDBE11
71
FMIADDR10
O
Adress data 10 (for flash )
FMIADDBE10
72
FMIADDR9
O
Adress data 9 (for flash )
FMIADDBE9
73
FMIADDR8
O
Adress data 8 (for flash )
FMIADDBE8
74
FMIADDR7
O
Adress data 7 (for flash )
FMIADDBE7
75
FMIADDR6
O
Adress data 6 (for flash )
FMIADDBE6
76
FMIADDR5
O
Adress data 5 (for flash )
FMIADDBE5
77
FMIADDR4
O
Adress data 4 (for flash )
FMIADDBE4
78
FMIADDR3
O
Adress data 3 (for flash )
FMIADDBE3
79
FMIADDR2
O
Adress data 2 (for flash )
FMIADDBE2
80
FMIADDR1
O
Adress data 1 (for flash )
FMIADDBE1
81
FMIADDR0
O
Adress data 0 (for flash )
FMIADDBE0
52
NOT_FMICSD
O
Chip select D
TL
51
NOT_FMICSC/ADDR24
O
Chip select C
TL
50
NOT_FMICSB
O
Chip select B
CIEN
49
NOT_FMICSA
O
Chip select A
NFMICSA
88
NOT_FMIOE
O
Output enable
NFMIOE
86
NOT_FMIBE1
O
Byte enable 1
NOTBEI
87
NOT_FMIBE0
O
Byte enable 0
TL
85
NOT_FMILBA
O
Flash device load burst address
NFMILBA
83
FMIRDNOTWR
O
Read not write
FMIRDNWR
82
FMIWAIT
I
Wait input (extend read/write cycle)
FMI WAIT
53
FMIFLASHCLK
O
Peripheral clock
TL
SDRAM interface for LMI (Local Management Interface)
201
LMIDATA15
I/O
Bidirectional data 15 (for SDRAM )
LMIDBE15
199
LMIDATA14
I/O
Bidirectional data 14 (for SDRAM )
LMIDBE14
198
LMIDATA13
I/O
Bidirectional data 13 (for SDRAM )
LMIDBE13
197
LMIDATA12
I/O
Bidirectional data 12 (for SDRAM )
LMIDBE12
194
LMIDATA11
I/O
Bidirectional data 11 (for SDRAM )
LMIDBE11
192
LMIDATA10
I/O
Bidirectional data 10 (for SDRAM )
LMIDBE10
191
LMIDATA9
I/O
Bidirectional data 9 (for SDRAM )
LMIDBE9
190
LMIDATA8
I/O
Bidirectional data 8 (for SDRAM )
LMIDBE8
180
LMIDATA7
I/O
Bidirectional data 7 (for SDRAM )
LMIDBE7
178
LMIDATA6
I/O
Bidirectional data 6 (for SDRAM )
LMIDBE6
175
LMIDATA5
I/O
Bidirectional data 5 (for SDRAM )
LMIDBE5
174
LMIDATA4
I/O
Bidirectional data 4 (for SDRAM )
LMIDBE4
171
LMIDATA3
I/O
Bidirectional data 3 (for SDRAM )
LMIDBE3
169
LMIDATA2
I/O
Bidirectional data 2 (for SDRAM )
LMIDBE2
168
LMIDATA1
I/O
Bidirectional data 1 (for SDRAM )
LMIDBE1
167
LMIDATA0
I/O
Bidirectional data 0 (for SDRAM )
LMIDBE0
206
LMIADDR12
O
Adress data 12 (for SDRAM )
LMIABE12
209
LMIADDR11
O
Adress data 11 (for SDRAM )
LMIABE11
157
LMIADDR10
O
Adress data 10 (for SDRAM )
LMIABE10
210
LMIADDR9
O
Adress data 9 (for SDRAM )
LMIABE9
211
LMIADDR8
O
Adress data 8 (for SDRAM )
LMIABE8
213
LMIADDR7
O
Adress data 7 (for SDRAM )
LMIABE7
214
LMIADDR6
O
Adress data 6 (for SDRAM )
LMIABE6
215
LMIADDR5
O
Adress data 5 (for SDRAM )
LMIABE5
216
LMIADDR4
O
Adress data 4 (for SDRAM )
LMIABE4
150
LMIADDR3
O
Adress data 3 (for SDRAM )
LMIABE3
152
LMIADDR2
O
Adress data 2 (for SDRAM )
LMIABE2
153
LMIADDR1
O
Adress data 1 (for SDRAM )
LMIABE1
154
LMIADDR0
O
Adress data 0 (for SDRAM )
LMIABE0
159
LMIBA1
O
Bank select 1
LMIBABE1
160
LMIBA0
O
Bank select 0
LMIBABE0
182
LMIDQM0
O
Data I/O mask lower
LMIDQMBE0
186
LMIDQM1
O
Data I/O mask upper
LMIDQMBE1
181
LMIDQS0
O
Data strobe lower (DDR). Not used when SDR connected to LMI
LMIDQSBE0
188
LMIDQS1
O
Data strobe upper (DDR). Not used when SDR connected to LMI
LMIDQSBE1
162
NOT_LMICS
O
Chip select
NLMICSBE
163
NOT_LMIRAS
O
Latch row address strobe
NLMIRASBE
Pin No.
Pin Name
I/O
Pin Function
sheet name
LC-19D1E/S-BK/WH
5 – 18
Peripherals
Asynchronous serial controller(ASC)
164
NOT_LMICAS
O
Latch column address strobe
NLMICASBE
206
LMICLKEN
O
Clock enable
LMICLKENBE
203
LMICLKEN
O
Clock LMICLKBE
202
NOT_LMICLK
O
inverted clock(DDR). Not used when SDR connected to LMI
LMINCLKBE
183
LMI_VREF
I
Input reference voltage (DDR). Connected to ground when SDR
is connected to LMI.
is connected to LMI.
LMIVREF
166
LMIRDNOTWR
O
Write enable signal.
LMIRDNWRBE
Audio INTERFACE
Analog audio DAC pins
Analog audio DAC pins
28
OUTLMINUS
O
Audio DAC left differential current output
RIGHTM
24
OUTRMINUS
O
Audio DAC right differential current output
LEFTM
29
OUTLPLUS
O
Audio DAC left differential current output
RIGHTP
25
OUTRPLUS
O
Audio DAC right differential current output
LEFTP
23
VBGOUT
O
Audio DAC filtered output reference voltage
C-GND
26
IREFDAC
I
Current reference for Audio DAC
R-GND
Digital audio pins
37
S/PDIF
O
Digital audio
TL
Video interface
15
VDAC1OUT
O
Video DAC output 1
R
16
VDAC2OUT
O
Video DAC output 2
G
17
VDAC3OUT
O
Video DAC output 3
B
18
VDAC4OUT
O
Video DAC output 4
CVBS
14
GNDREXTVDAC
I
Video DAC external resister ground
GND
13
REXTVDACRGB
I
VDAC external resister input
R-GND
pin
Alternative function
I/O
Description
Usual assignment
sheet name
126
ASC0_NOTOE
O
ASC0_NOTOE
PIO0[6]
TSSWITCH
118
ASC0_TXD
O
ASC0 transmit data signal
PIO0[0]
CARDVC-
COC
COC
119
ASC0_RXD
I
ASC0 receive data signal
PIO0[1]
VCCEN
122
ASC0_RTS
O
ASC0 request to send signal
PIO0[4]
NOTRE-
SETCI
SETCI
123
ASC0_CTS
I
ASC0 clear to send signal
PIO0[5]
NOTREADY
108
ASC1_TXD
O
ASC1 transmit data signal
PIO2[0]
TXD1
109
ASC1_RXD
I
ASC1 receive data signal
PIO2[1]
RXD1
110
ASC1_RTM
O
ASC1 request to send signal
PIO2[2]
IRQ
111
ASC1_CTS
I
ASC1 clear to send signal
PIO2[3]
TL
Smartcards pin mapping
122
SC0_RESET
SC0 reset signal
PIO0[4]
NOTRE-
SETCI
SETCI
123
SC0_COMD_VCC
SC0_command_VCC
PIO0[5]
NOTREADY
126
SC0_DIR
SC0_directry
PIO0[6]
127
SC0_DETECT
SC0_detection
PIO0[7]
FERESET
118
SC0_DATAOUT
Serial data output
PIO0[0]
CARDVC-
COC
COC
119
SC0_DATAIN
Serial data input
PIO0[1]
VCCEN
120
SC0_CG_EXTCLK
External clock
PIO0[2]
TL
121
SC0_CG_CLK
Clock for smartcard from system clock
PIO0[3]
FLASHWP
122
SYSRV_SC_RESET_0
Reset to card
PIO0[4]
NOTRE-
SETCI
SETCI
123
SYSRV_SC_POWER_0
Smartcard power
PIO0[5]
NOTREADY
127
SYSRV_SC_DETECT_0
Smartcard detection
PIO0[7]
FERESET
118
SC0_DATAINOUT
Serial data output
PIO0[0]
CARDVC-
COC
COC
121
SC0_FSCLK0
Clock for smartcard from smartcard FS
PIO0[3]
FLASHWP
Synchronous serial controller pin mapping
5
SSC0_SCLKINOUT
O
Serial clock in
PIO3[1]
I2CSCL
4
SSC0_MTSR_DINOUT
I
Serial data input for SSC0: master transmit, slave receive
PIO3[0]
I2CSDA
119
SSC1_MRST_DINOUT
O
Serial data for SSC1: master receive, slave transmit
PIO0[1]
VCCEN
120, 7
SSC1_SCLKINOUT
O
Serial clock in
PIO0[2], PIO3[3]
TL, TVSCL
126, 6
SSC1_MTSR_DINOUT
I
Serial data input for SSC1: master transmit, slave receive
PIO0[6], PIO3[2]
TSSWITCH,
TVSDA
TVSDA
Programable I/O pins
Pin No.
Pin Name
I/O
Pin Function
sheet name
LC-19D1E/S-BK/WH
5 – 19
127
PIO0[7]
I/O
PIO port 0 [7]
FERESET
126
PIO0[6]
I/O
PIO port 0 [6]
TSSWITCH
123
PIO0[5]
I/O
PIO port 0 [5]
NOTREADY
122
PIO0[4]
I/O
PIO port 0 [4]
NOTRE-
SETCI
SETCI
121
PIO0[3]
I/O
PIO port 0 [3]
FLASHWP
120
PIO0[2]
I/O
PIO port 0 [2]
TL
119
PIO0[1]
I/O
PIO port 0 [1]
VCCEN
118
PIO0[0]
I/O
PIO port 0 [0]
CARDVC-
COC
COC
46
PIO1[7]
I/O
PIO port 1 for card (parallel)
FEERROR
45
PIO1[6]
I/O
PIO port 1 for card (parallel)
TSOUTD6
44
PIO1[5]
I/O
PIO port 1 for card (parallel)
TSOUTD5
43
PIO1[4]
I/O
PIO port 1 for card (parallel)
TSOUTD4
41
PIO1[3]
I/O
PIO port 1 for card (parallel)
TSOUTD3
40
PIO1[2]
I/O
PIO port 1 for card (parallel)
TSOUTD2
39
PIO1[1]
I/O
PIO port 1 for card (parallel)
TSOUTD1
38
PIO1[0]
I/O
PIO port 1 for card (parallel)
TSOUTD0
117
PIO2[7]
I/O
PIO port 2 [7]
TL
116
PIO2[6]
I/O
PIO port 2 [6]
TL
115
PIO2[5]
I/O
PIO port 2 [5]
TL
114
PIO2[4]
I/O
PIO port 2 [4]
IR
111
PIO2[3]
I/O
PIO port 2 [3]
TL
110
PIO2[2]
I/O
PIO port 2 [2]
IRQ
109
PIO2[1]
I/O
PIO port 2 [1]
RXD1
108
PIO2[0]
I/O
PIO port 2 [0]
TXD1
12
PIO3[6]
I/O
PIO port 3 [6]
NOTIORD
11
PIO3[5]
I/O
PIO port 3 [5]
NOTIOWR
10
PIO3[4]
I/O
PIO port 3 [4]
CARDDET
7
PIO3[3]
I/O
PIO port 3 [3]
TVSCL
6
PIO3[2]
I/O
PIO port 3 [2]
TVSDA
5
PIO3[1]
I/O
PIO port 3 [1]
I2CSCL
4
PIO3[0]
I/O
PIO port 3 [0]
I2CSDA
Miscellaneous
114
IRB_UHF_IN
I
UHF channel input for IRB
PIO2[4]
IR
115
IRB_PPM_OUT
O
PPM output of IRB
PIO2[5]
TL
114
IRB_PPM_IN
I
PPM input of IRB
PIO2[4]
IR
115
PCM_DATAOUT
O
PCM data output
PIO2[5], alt1
TL
116
PCM_LRCLKOUT
O
PCM LR clock output
PIO2[6], alt1
TL
117
PCM_SCLKOUT
O
PCM S clock output
PIO2[7], alt1
TL
116
FDMA_REQ_0
O
Frequency division multiple access
PIO2[6], alt0
TL
117
FPRESET
I
FP_reset signal
PIO2[7], alt0
TL
10
EXTINT2
I
External input 2
PIO3[4], alt0
CARDDET
11
EXTINT1
I
External input 1
PIO3[5], alt0
NOTIOWR
12
EXTINT0
I
External input 0
PIO3[6], alt0
NOTIORD
4
DMAREQ(0)
O
Direct Memory Access request (0)
PIO3[0], alt2
I2CSDA
5
DMAREQ(1)
O
Direct Memory Access request (1)
PIO3[1], alt2
I2CSCL
6
EXT_INT_OUT(0)
O
External input_output (0)
PIO3[2], alt2
TVSDA
7
EXT_INT_OUT(1)
O
External input_output (1)
PIO3[3], alt2
TVSCL
Debug link
JTAG test access port (TAP) pins
JTAG test access port (TAP) pins
134
TDI
I
TAP boundary scan test data input
TDI
133
TMS
I
TAP boundary scan test mode input
TMS
137
TCK
I
TAP boundary scan test clock
TCK
135
NOT_TRST
I
TAP boundary scan test logic reset
NOTTRST
132
TDO
O
TAP boundary scan test data output
TDO
DCU pins
1
DCUTRIGGERIN
I
External trigger input to DCU
TRIGIN
2
DCUTRIGGEROUT
O
Signal to trigger external debug circuitry
TRIGOUT
pin
Alternative function
I/O
Description
Usual assignment
sheet name
LC-19D1E/S-BK/WH
5 – 20
2.11. IC4201 (RH-iXB765WJZZ)
2.11.1 Block Diagram
2.11.2 Pin Connections and short description
256Mb DDR SDRAM
Pin No.
Pin Name
I/O
Pin Function
45,46
CK, CK
I
Clock : CK and CK are differential clock inputs.
All address and control input signals are sampled on the positive edge of CK and negative edge of CK.
Output (read) data is referenced to both edges of CK.
Internal clock signals are derived from CK/CK.
All address and control input signals are sampled on the positive edge of CK and negative edge of CK.
Output (read) data is referenced to both edges of CK.
Internal clock signals are derived from CK/CK.
44
CKE
I
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH operction(all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK,CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up,
After VREF has become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
buffers and output drivers.
Taking CKE Low provides PRECHARGE POWER DOWN and SELF REFRESH operction(all bank idle)
CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit, and for output disable.
CKE must be maintained high throughput READ and WRITE accesses.
Input buffers, excluding CK,CK and CKE are disabled during POWER-DOWN.
Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS Low level after Vdd is applied upon 1st power up,
After VREF has become stable during the power on and initialization sequence, it must be maintained
for proper operation of the CKE receiver.
For proper SELF-REFRESH entry and exit, VREF must be maintained to this input.
24
CS
I
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.
All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.
All commands are masked when CS is registered HIGH.
CS provides for external bank selection on systems with multiple banks.
CS is considered part of the command code.
21-23
RAS, CAS, WE
I
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
20,47
LDM,(UDM)
I
Input Data Mask : DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15.
DM may be driven high, low, or floating during READs.
Input data is masked when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15.
DM may be driven high, low, or floating during READs.
26,27
BA0, BA1
I
Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ,WRITE or PRECHARGE
command is being applied.
command is being applied.
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