Sharp 32KF-84H (serv.man14) Service Manual ▷ View online
59
32KF-84H
SDA9380 (IC6006)
Block Diagram
VSYNC
HSYNC
HSYNC
CONTROL
PLL
CLL
HPROT
VBLO
X1
X2
X2
VREFC
SCL
SDA
TEST
CLKI
PROTECTION
START UP
H-OUT
V-OUT
EW-OUT
AVERAGE
BEAM LIMITER
HD
VD+
VD-
VD-
E/W
φ2
φ2
φ2
φ2
VPROT
SSD
IBEAM
H35K
RESN
SWITCH
D/A
BSOIN
H38K
VREFH
VREFN
HSAFE
PW/PH-CORR
CLAMP
CLAMP
CLAMP
BLACK
STRETCH
SATURATION
CONTROL
CUT OFF +
WHITE POINT
OUTPUT
BUFFER
RGB
MATRIX
BRIGHTNESS
CONTROL
DELAY
RGB/YUV 1
RGB 2
3
3
3
3
FBL 2
FBL 1
FBL 1
DCI
ROUT
GOUT
BOUT
GOUT
BOUT
YUV/RGB 0
3
3
3
3
Y
SVM
CLEXT
VDD(A1..4)
VSS(A1..4)
VDD(D1..2)
VSS(D1..2)
VDD(MC)
VSS(MC)
SUBST
PWM
PWM
MATRIX
MATRIX
MEASURE
PULSES
3
2
3
3
3
YUV
YUV
Y
UV
UV
3
3
3
PEAK DRIVE
LIMITER
BLUE STRETCH
CONTRAST
CONTROL
SWITCH
MATRIX
3
YUV
FH1_2
SCP
I²C
PROTON
60
32KF-84H
SDA9380 (IC6006)
Pin Description
Pin No.
Name
Type
Description
1
CLKI
I/TTL
Input for external line locked clock *)
2
X2
Q
Reference oscillator output, Crystal
3
X1
I
Reference oscillator input, Crystal
4
CLEXT
I/TTL
Switching between internal (L) and external clock (H) *)
5
TEST
I/TTL
Switching between normal operation (TEST=L) and test mode
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio-
nal test pins)
6
SUBST
S
Substrate pin, has to be connected to ground whenever a
power supply or signal is applied
power supply or signal is applied
7
RESN
I/TTL
Reset input, active Low
8
SCL
I
I²C Bus clock
9
SDA
IQ
I²C Bus data
10
VDD(D)
S
Digital supply
11
VSS(D)
S
Digital ground
12
HD
Q
Control signal output for H driver stage (open drain)
13
H35K
Q/TTL
Goes High when frequency of HSYNC is about 35kHz or more
14
H38K
Q/TTL
Goes High when frequency of HSYNC is about 38kHz
15
PWM
Q/TTL
Pulse width modulated control signal output
16
VSYNC
I/TTL
V-sync input
17
FH1_2
I/TTL
Switching between 1f
H
mode (L) and 2f
H
mode (H)
18
HSYNC
I
HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
19
VDD(A1)
S
Analog supply
20
VSS(A1)
S
Analog ground
21
Φ
2
I
Line flyback for H-delay compensation
22
VDD(A2)
S
Analog supply
23
VSS(A2)
S
Analog ground
24
E/W
Q
Control signal output for East-West raster correction
25
D/A
Q
Output of an I²C Bus controlled DC voltage
26
VD+
Q
Control signal output for DC coupled V-output stage
27
VD-
Q
Like VD+
28
VDD(A3)
S
Analog supply
29
VSS(A3)
S
Analog ground
30
VPROT
I
Watching external V-output stage (input is the V-saw-tooth from
feedback resistor)
feedback resistor)
31
HPROT
I
Watching EHT (input is e.g. H-flyback)
32
HSAFE
I
Watching B+ when frequency of HD has to be decreased
33
BSOIN
I
Input for starting Black Switch-Off
34
IBEAM
I
Input for a beam current dependent signal for stabilization of
width, height and H-phase
width, height and H-phase
35
PROTON
Q/TTL
Protection on (goes High after response of H- or V-protection)
61
32KF-84H
*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz line frequency.
36
VREFH
IQ
Reference voltage
37
VBLO
Q/TTL
Vertical blanking output
38
VREFN
IQ
Ground for VREFH
39
VREFC
I
Reference current input
40
DCI
I
Dark current input for cut off and white level control
41
VDD(A4)
S
Analog supply
42
Y/R 0
I
Luminance or R input
43
U/G 0
I
U signal or G input
44
V/B 0
I
V signal or B input
45
VSS(A4)
S
Analog ground
46
R/Y 1
I
First R or Y input for insertion
47
G/U 1
I
First G or U input for insertion
48
B/V 1
I
First B or V input for insertion
49
FBL1
I
Fast blanking input for RGB1
50
FBL2
I
Fast blanking input for RGB2
51
R2
I
Second R input for insertion
52
G2
I
Second G input for insertion
53
B2
I
Second B input for insertion
54
VDD(MC)
S
Analog supply for RGB output stage
55
ROUT
Q
R output
56
GOUT
Q
G output
57
BOUT
Q
B output
58
SCP
Q
Blanking signal with H- and color burst component
(V-component selectable by I²C Bus)
(V-component selectable by I²C Bus)
59
VSS(MC)
S
Analog ground for RGB output stage
60
SVM
Q
Luminance output for scan velocity modulation circuit
61
VDD(D)
S
Digital supply
62
VSS(D)
S
Digital ground
63
SSD
I/TTL
Disables softstart
64
SWITCH
Q/TTL
Output of an I²C Bus controlled switch (register 00, bit SW)
Pin No.
Name
Type
Description
SDA9380 (IC6006)
Pin Description
62
32KF-84H
PRIMUS
VSP 9402A
VSP 9432A
VSP 9432A
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
vdddacy
ayout
auo
ut
a
v
out
vssdacy
vssd2
vddd2
sda
tms
vssp2
vddp2
scl
v
hout
h50
adr/tdi
v50
(reserved)
bin1
vddargb
vssargb
vdd33rgb
rin2
gin2
bin2
vddac1
vssac1
cvbs1
cvbs2
cvbs3
cvbs4
vdd33c
vss33c
vss33rgb
cvbso1
vdda
c
2
vssac2
vd
dd1
vss
d
1
vdd
apll
xou
t
xin
vd
dp1
vss
p
1
vdd
dacv
vss
d
a
cv
vddd
acu
vssdacu
gin1
ri
n
1
fb
l2
fb
l1
v
s
s
af
bl
vd
dafbl
vssd4
vdd
d4
v
ssd3
vdd
d3
clkou
t
v
ssp3
vdd
p3
vou
t
reset
cvbs5
cvbs6
cvbs7
cvbso2
cvbso3
656clk
656io7
656io6
656io5
656io5
656
io4
656
io3
656
io1
65
6io0
65
6hin/c
lkf2
0
656vin/blank
tcl
k
65
6io2
SDA9380 (IC6006)
Pin Assignments
VSP9402A (IC6007)
Pin Assignments
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SDA 9380
64 63 62 61 60 59 58 57 56 55 54 53
51
52
50 49
17 18 19 20 21 22 23 24 25 26 27 28
30
29
31 32
X2
X1
CLEXT
TEST
VSS
(D
)
CLKI
FB
L
2
FB
L
1
V
D
D(
D)
SVM
B/V 1
SSD
R2
G2
B2
VD
D
(M
C
)
RO
UT
GOU
T
BO
U
T
SC
P
VSS
(M
C
)
SUBST
RESN
SCL
SDA
VDD(D)
VSS(D)
HD
H35K
H38K
PWM
FH
1
_
2
G/U 1
R/Y 1
SWI
T
C
H
V/B 0
U/G 0
U/G 0
Y/R 0
VSS(A4)
VDD(A4)
DCI
VREFC
VREFN
VBLO
VREFH
PROTON
IBEAM
BSOIN
VSYNC
H
SYN
C
VD
D
(A1)
VS
S(
A1
)
VD
D
(A2)
VS
S(
A2
)
E/
W
H
SAF
E
HP
R
O
T
VP
R
O
T
VS
S(
A3
)
VD
D
(A3)
VD
-
VD
+
D/
A
Φ
=
2
Click on the first or last page to see other 32KF-84H (serv.man14) service manuals if exist.