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The detected video signal is output from pins 18 of IC403, to sound traps Z403/404. The video is taken from the other
side via the appropriate filter to Pin 18 of IC403. (1.2 p to p) Video to the Scart connectors is taken after R458 to Pin 19
of the Scart connector. The CVBS_TXT output Pin29 output is fed to IC501 Pin 34 (for Teletext). The video signal is
sometimes labelled CVBS on the circuit diagram. This stands for Composite Video Blanking & Sync.
The composite signal is input Pin 13 (Video input) of IC403. This IC carries out all of the luma/Chroma processing
internally and also provides the customer control functions of brightness, contrast, sharpness and saturation. IC403 is
I²C bus controlled and incorporates auto greyscale circuitry and internal luma/chroma delay lines. The resulting R.G.B
drive is output on pins 30,31 and 32. The R.G.B passes via connector PL405 to the CRT base PCB. Here the R.G.B
signal is amplified by IC901 to provide drive for the cathodes of the CRT. IC901 produces a feedback signal, which is
fed to IC403 (pin 33) for blanking and auto greyscale correction.

The demodulated mono sound is taken from pin 55 of IC403 directly to the sound output stage IC401 Pin 7. The output
signal from IC401 is Volume controlled achieved within IC403 using the I²C bus line from IC501. To limit the volume at
the specified out put the A_out pin 55 is fed to IC 401 through a voltage divider R455 and R454. Muting of the output
stage is provided from Pin 46 of IC501 to pin3 of IC401/6 of IC301.
IN the stereo model the IF from PINS 10 & 11 of the tuner passes through Z401 and the output signal goes through pins
1&2 of IC403. The output QSS signal from IC 403 is taken from pin 11 and sent to audio processor IC700. The left
channel is output on PIN 29 and the right channel output is on PIN 28. Then to IC301 after passing through a voltage
divider R454/R455 for the right channel and R463/R464 for the left channel.
IC403 handles also the AM modulated signals in L/L’ systems at pins 1&2.

2.12.1 Video and Sound
IC403 has three CVBS inputs at pins 18,20 and 22.The composite video signal of AV1 is taken from pin 20 of the
Scart connector to pin 20 of IC403. The mono sound signal is taken from pins 2 and 6 of the Scart sockets to the
switching transistors Q101. The transistor switches the audio depending on the source, and is then fed to pin14 of
lC403.
When AV input is selected pin 5,6,7 of the microprocessor IC50I is taken high, this switches the IC403 to external
input mode via I²C BUS. This connects the video inputs on pins 20 or 22 to IC403 and the audio input on pin 14 to
the audio out on pin 55 (via the internal volume control circuit) The signal paths are then as for videopath.
The chassis can detect the video signals on Scart using pin 8 switching voltage at pin 56 of IC501.

2.12.2 R.G.B
The R.G.B signals from pins 7,11 and 15 of the Scart connector are fed to the R.G.B input pins (25,26,27) of
IC403.
R.G.B operation can be enabled by either taking pin 16 of the Scart connector high, this high is fed to Pin 28 of
IC403, or via the l²C bus the microprocessor sets IC403 to forced R.G.B mode in which the video processor
generates its own fast blank signal. This puts the IC into external R.G.B mode and selects the inputs on pins 25,26
and 27, overriding the video input on pin 20/22.
Note: when using R.G.B input the contrast, brightness and colour controls will still operate.

Either a PLL or a VST tuner is used as a tuner.
UV1316 (VHF/UHF) is used as a PLL tuner. For only PALM/N, NTSC M applications UV 1336 is used as the PLL
tuner. UV 1315 (VHF/UHF) is used as a VST Tuner.

OFF-AIR CHANNELS 

CABLE CHANNELS 

FREQUENCY FREQUENCY 

BAND 

 

CHANNELS 

RANGE (MHz) 

CHANNELS 

RANGE (MHz) 

Low Band 

E2 to C 

48.25 to 82.25 (1) 

S01 to S08 

69.25 to 154.25 

Mid Band 

E5 to E12 

175.25 to 224.25 

S09 to S38 

161.25 to 439.25 

High Band 

E21 to E69 

471.25 to 855.25 (2) 

S39 to S41 

447.25 to 463.25 

(1). Enough margin is available to tune down to 45.25 MHz.

(2). Enough margin is available to tune up to 863.25 MHz.

Typical

 Max.

Min.    Typical

Max.

Low band: 5 dB

9 dB

All channels:

38 dB    44 dB

52 dB

Mid band:

5dB

9 dB

Gain Taper (of-air channels):

8 dB

High band: 6 dB

9 dB

BAND CHANNELS  FREQUENCY 

RANGE (MHz) 

Low Band 

2 to D 

55.25 to 139.25 

Mid Band 

E to PP 

145.25 to 391.25 

High Band 

QQ to 69 

397.25 to 801.25 

Noise is typically 6 dB for all channels. Gain is minimum 38 dB and maximum 50 dB for all
channels.

           

OFF-AIR CHANNELS 

CABLE CHANNELS 

FREQUENCY FREQUENCY 

BAND 

CHANNELS 

RANGE (MHz) 

CHANNELS 

RANGE (MHz) 

Low Band 

E2 to C 

48.25 to 82.25 (1) 

S01 to S10 

69.25 to 168.25 

Mid Band 

E5 to E12 

175.25 to 224.25 

S11 to S39 

231.25 to 447.25 

High Band 

E21 to E69 

471.25 to 855.25 (2) 

S40 to S41 

455.25 to 463.25 

(1). Enough margin is available to tune down to 45.25 MHz.
(2). Enough margin is available to tune up to 863.25 MHz.

Typ.  Max.

 Min.     Typ.

Max.

Low band

6 dB 9 dB

All Channels

38 dB     44 dB

50 dB

Mid band

6 dB 10 dB

Gain Taper

8 dB

High band 6 dB 11 dB

(off-air channels)

The MSP 34x0G is designed to perform demodulation of FM or AM-Mono TV sound.
Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or the satellite specs can be
processed with the MSP 34x0G. Only the MSP 3410 does digital demodulation and decoding of NICAM-coded TV
stereo sound. The MSP 34x0G offers a powerful feature to calculate the carrier field strength which can be used for
automatic standard detection (terrestrial) and search algorithms (satellite).

TDA7266L is used as the AF output amplifier for mono applications. It is supplied by +12 VDC coming from a  separate
winding in the SMPS transformer. An output power of 4 W (THD = 0.5 %) can be delivered into an 16 ohm load.
TDA7266 is used as the AF output amplifier for stereo applications. It is supplied by +12 VDC coming from a separate
winding in the SMPS transformer. An output power of 2*4W (THD = 0.5 %) can be delivered into an 16 ohm load.

The TDA8174A is a power amplifier circuit for use in 90° and 110° color deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes.
IC403 generates a vertical pulse signal VER_OUT and V_AMP that are fed to IC600 (the vertical stage IC). IC600 is
supplied by a 26V DC via diode D610. It generates its own ramp signal and based on the V_AMP & VER_OUT signals
it produces the vertical deflection signals that are fed to connector PL601. Vertical linearity adjustment is controlled by
Q604, which is driven by the PWM output of IC501 at pin 49. Vertical position adjustment is conducted by Q606 derived
by the VER_OUT signal. Switching Q606 will change the DC voltage on VOUT_2 pin, which will either lower or higher
the picture. A DC level is supplied at VOUT_2 via D614 to stabilise the picture and make its position changeable.

The TDA6107JF includes three video output amplifiers and is intended to drive the three cathodes of a colour CRT
directly. The device is contained in a plastic DIL-bent-SIL 9-pin medium power (DBS9MPF) package, and uses high-
voltage DMOS technology. To obtain maximum performance, the amplifier should be used with black-current control.

The DC voltage required at various parts of the chassis are provided by an SMPS transformer controlled by the IC
MC44608 which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer produces

126 V (Flat models) or 116 V (non Flat models)

 for FBT input, +/- 14 V for audio output IC, S + 3.3, S + 5 V and 8 V for

ST92195.

The ZX series of receivers incorporate a Motorola switch mode power supply using a MC 44608 regulator controller
IC. The circuit provides power to the receiver in both standby and normal operation modes.

The switch on the mains supply is fed through the mains filter network TR801, the surge limiter resistor R828, the bridge
rectifier diodes D811/13/37/38, and reservoir capacitor producing approx. 320 volts D.C. to feed the switching MOSFET
Q801 via the primary winding of TR802 pins 6 and 7.
Start up resistor R801 feeds from a 500V coming from the mains through the adder diodes D809, D890 to pin 8 of
IC800, the IC uses 9mA current source and connects it internally to VCC at pin6 allowing a rapid charge enough for
start up.  Then IC800 responds with the oscillator starting to oscillate at a 40 KHz frequency fixed by the IC manufac-
turer.
The IC then produces, pulse width modulation pulses, at this frequency on pin 5 to drive the base of the switching FET
Q801, that will then switch current on and off through the primary of TR802, which will in turn provides voltages in the
secondary windings. The secondary winding voltages being proportional to the length of time that Q801 is turned on in
each cycle. The voltage produced between pins 4 and 3 of TR802 is rectified by D804 developing aprox. 12 volts on
C810, which takes over from the start up resistor to supply pin 8 of IC800.
The Demag pin at pin1 offers 3 different functions: Zero voltage crossing detection (50mV), 24mA current detection and
120mA current detection. The 24mA level is used to detect the secondary reconfiguration status and the 120mA level
to detect an Over Voltage status called Quick OVP.
The VCC at pin6 operates between 6,6V and 13V in normal operation, when this voltage exceeds 15V then the IC
output is disabled.

After initial start up the secondary voltages of TR802 are established. These voltages then need to be regulated to the
required levels. In a switch mode power supply such as this, it is the ON time of the switching FET Q801 that determines
the output voltages produced. To provide regulation of the supply there is a feedback loop via an adjustable zener
IC118 and an OPTO- coupler connected to pin3 of IC800. The reference voltage of IC118 is set to 2,5V to supply a B+
voltage of 115V. Any fluctuation at this pin will cause IC800 to compensate it either by increasing or decreasing the
voltage at the secondary outputs.

The MC44608 offers two OVP functions:
1- A fixed function that detects when V CC is higher than 15.4V
2- A programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared
to the reference current Iovp (120mA). -Thus this OVP is quicker than normal number one as it directly senses the
change in current rather than waiting for a specific voltage value, and is called QOVP. In both cases, once an OVP
condition is detected, the output is latched off until a new circuit START–UP.
3- A software controlled function acts on pin52 of IC501. This pin monitors feedback from both 8V and 5V via D512,
then compares these to a reference value Vref pre-set by the hardware through resistors R545, R546, R548. In normal
mode operation 1.2V < Vref < 2.4V. Any voltage outside this window will cause the micro controller to force the TV to
stand by mode by lowering the standby port. Refer to standby mode.

To monitor the current drawn by the receiver the source of Q801 is returned to the bridge rectifier through a low value
resistor R807. All the current drawn by the receiver will flow through that resistor each time Q801 conducts; this will
produce a voltage across the resistors proportional to the current drawn by the receiver. This voltage is fed to pin 2 of
IC800 via R806. When the receiver is working normally the voltage across R807 is only a fraction of a volt and is not
large enough to have any effect on IC800. Under fault conditions, if the receiver draws excessive current the voltage
across R807 will rise. This voltage is monitored by the current sense input pin2.

This Current Sense pin senses the voltage developed on the series resistor R806 inserted in the source of the power
MOSFET. When I sense reaches 1V, the Driver output (pin 5) is disabled. This is known as the Over Current Protection
function. A 200mA current source is flowing out of the pin 3 during the start–up phase and during the switching phase
in case of the Pulsed Mode of operation. A resistor can be inserted between the sense resistor and the pin 3, thus a
programmable peak current detection can be performed during the SMPS stand–by mode.

As mentioned earlier the Start–up Management of MC44608 is as follows:
The Vi pin 8 of IC800 is directly connected to the HV DC rail Vin. This high voltage current source is internally connected
to the VCC pin and thus issued to charge the VCC capacitor. The V CC capacitor charge period corresponds to the
Start–up phase. When the V CC voltage reaches 13V, the high voltage 9mA current source is disabled and the device
starts working. The device enters into the switching phase.
To help increase the application safety against high voltage spike on pin8 a small wattage 1k _ series resistor is inserted
between the Vin rail and pin 8. After this start-up the IC can distinguish between the different modes of operation using
the following technique:

The LW latch is the memory of the working status at the end of every switching sequence. Two different cases must be
considered for the logic at the termination of the SWITCHING PHASE:
1. No Over Current was observed
2. An Over Current was observed
These two cases correspond to the two signals “NOC” in case of “No Over Current” and “OC” in case of Over Current.
The effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current, and
Q=0 for over current.
To enter the standby mode secondary side is reconfigured using D889 loop, this starts with the microprocessor ‘s pin 47
becomes high; as the standby port becomes high Q503 conducts and Q802 becomes off then D889 conducts and the
high voltage output value becomes lower than the NORMAL mode regulated value. The shunt regulator IC118 is fully
OFF. In the SMPS stand–by mode all the SMPS outputs are lowered except for the low voltage output that supply the
wake–up circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed by
the Zener diode (D801) connected in parallel to the TL431. The secondary reconfiguration status can be detected on
the SMPS primary side by measuring the voltage level at pin4 of TR802.
In the SMPS stand–by mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced. When VCC
crosses the current sense section, the C.S. clamping level depends on the power to be delivered to the load during the
SMPS stand–by mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener
diode voltage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM
action. The proper SWITCHING PHASE termination must correspond to a NOC condition. The LW latch stores this
NOC status. The LATCHED OFF PHASE: The MODE latch is set.
The START–UP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The Stand-by signal is validated and the 200uA is sourced out of the Current Sense pin 2.

When the mains is switched OFF, so long as the electrolytic bulk capacitor provides energy to the SMPS the controller
remains in the switching phase. Then the peak current reaches its maximum peak value, the switching frequency
decreases and all the secondary voltages are reduced. The V CC voltage is also reduced. When VCC is less than 6,5V,
the SMPS stops working

Line and frame drive are generated by IC403. The sync pulses are separated from the incoming video signal at pin 18/
20/22 and used to control the internal circuitry of the IC. Line drive is produced by counting down the external 4.43 MHz
crystal at pin 40 to 15.625 KHz locked to the incoming sync. This drive is output on pin 48 and feeds directly to the line
drive transistor Q601. Note. That the output of IC403 Pin 48 is an open-collector and requires a pull up resistor, if the pin
is open circuited for test no waveform will be seen. Q601 collector feeds the line output transistor Q603.
The line output stage is conventional with a transformer containing a split diode winding for EHT generation. Fifth
harmonic tuning is achieved by capacitor C618/619.
A fly-back pulse is taken from pin 1 of the FBT transformer. This is required by IC403 (Pin 49) for burst / sync gating, and
RGB line blanking. The ver_sync signal is output from the pin47 and fed to Pin41 of IC501. The H_sync pulse is taken
from pin 1 of the FBT and fed to the micro at pin 40. These two signals are required by the micro for graphics timing and
also for text.