DOWNLOAD Sharp 21HS-50 (serv.man8) Service Manual ↓ Size: 4.5 MB | Pages: 44 in PDF or view online for FREE

1. The function of pin 20, 28, 29, 31, 32, 35 and 44 is dependent on the IC version (mono intercarrier FM demodulator

/ QSS IF amplifier and East-West output or not) and on some software control bits. The valid combinations are given
in table 1.

2. The vertical guard function can be controlled via pin 49 or pin 50. The selection is made by means of the IVG bit in

subaddress 2BH.

Pin functions for various versions

1. When additional (external) selectivity is required for FM-PLL system pin 32 can be used as sound IF input. This

function is selected by means of SIF bit in subaddress 28H.

2. The reference output signal is only available for the CMB1/CMB0 setting of 0/1. For the other settings this pin is a

switch output (see also table 67).

INSSW2

45

2

nd

 RGB / YUV insertion input

R2/VIN

46

2

nd

 R input / V (R-Y) input

G2/YIN

47

2

nd

 G input / Y input

B2/UIN

48

2

nd

 B input / U (B-Y) input

BCLIN

49

beam current limiter input / (V-guard input, note 2)

BLKIN

50

black current input / (V-guard input, note 2)

RO

51

Red output

GO

52

Green output

BO

53

Blue output

VDDA

54

analog supply of Teletext decoder and digital supply of TV-processor (3.3 V)

VPE

55

OTP Programming Voltage

VDDC

56

digital supply to core (3.3 V)

OSCGND

57

oscillator ground supply

XTALIN

58

crystal oscillator input

XTALOUT

59

crystal oscillator output

RESET

60

reset

VDDP

61

digital supply to periphery (+3.3 V)

P1.0/INT1

62

port 1.0 or external interrupt 1 input

P1.1/T0

63

port 1.1 or Counter/Timer 0 input

P1.2/INT0

64

port 1.2 or external interrupt 0 input

East-West Y/N

N

Y

N

Y

CMB1/CMB0 bits

00

01/10/11

00

01/10/11

00

01/10/11

00

01/10/11

AM bit

−

−

−

−

−

0

1

−

0

1

Pin 20

AVL

EWD

AVL

EWD

Pin 28

AUDEEM

SIFIN1

Pin 29

DECSDEM

SIFIN2

Pin 31

SNDPLL

SIFAGC

Pin 32

SNDIF

(1)

REFO

(2)

AVL/SNDIF

(1)

REFO

(2)

AMOUT

REFO

(2)

AMOUT

REFO

(2)

Pin 35

AUDEXT

AUDEXT QSSO AMOUT AUDEXT QSSO AMOUT

Pin 44

AUDOUT

controlled AM or audio out

ndbook, full pagewidth

SUPPLY

MANAGEMENT

internal

supply

UVLO

start

M-level

VCC

1

2

3

GND

S1

CTRL

FREQUENCY

CONTROL

VOLTAGE

CONTROLLED

OSCILLATOR

LOGIC

LOGIC

OVER-

VOLTAGE

PROTECTION

OVERPOWER
PROTECTION

short

winding

soft

start

S2

OVER-

TEMPERATURE

PROTECTION

S

Q

R

UVLO

Q

MAXIMUM

ON-TIME

PROTECTION

POWER-ON

RESET

−

1

VALLEY

100 mV

clamp

DRIVER

START-UP

CURRENT SOURCE

0.75 V

0.5 V

5

Isense

6

DRIVER

MGU230

4

DEM

8

DRAIN

7

HVS
n.c.

OCP

LEB

blank

Iss

2.5 V

burst
detect

  Block diagram.

V

CC

1

supply voltage

GND

2

ground

CTRL

3

control input

DEM

4

input from auxiliary winding for
demagnetization timing, OVP and OPP

I

sense

5

programmable current sense input

DRIVER

6

gate driver output

HVS

7

high voltage safety spacer, not
connected

DRAIN

8

drain of external MOS switch, input for
start-up current and valley sensing

handbook, halfpage

MGU231

1

2

3

4

VCC

GND

CTRL

DEM

DRAIN

HVS

DRIVER

Isense

8

7

6

5

  Pin configuration.

1

2

3

4

5

6

7

8

9

V

CC

Output

            GND

Output

Standby

Input

GND

N.C.

V

olume

Pin No.

Description

1

Vcc

2

Ch Output (+)

3

GND

4

Ch Output (-)

5

Standby

6

Ch Input

7

GND (Input)

8

N.C

9

Volume

Circuit Function Block Diagram

Pin Descriptions

Note: Do not apply voltage or current to NC pin from outside

Pin No.

Pin Name

1

Inverting Input

2

Power Supply

3

Pump-up Output

4

GND

5

Vertical Output

6

Vertical Output Power Supply

7

Non-inverting Input

Pin Descriptions

Non-inverting Input

Output Vcc

Output

GND

Pump Up Out

Vcc

Inverting Input

1

2

3

4

5

6

7

Pump Up

Thermal Protection

Amp

+

-

Circuit Function Block Diagram

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.

T

A

Ambient Operating Temperature

–

0

70

°C

T

S

Storage Temperature

–

−40

125

°C

V

SUP1

First Supply Voltage

AHVSUP

−0.3

9.0

V

V

SUP2

Second Supply Voltage

DVSUP

−0.3

6.0

V

V

SUP3

Third Supply Voltage

AVSUP

−0.3

6.0

V

dV

SUP23

Voltage between AVSUP 
and DVSUP

AVSUP,
DVSUP

−0.5

0.5

V

P

TOT

Package Power Dissipation
PSDIP64
PSDIP52
PQFP80
PLQFP64
PMQFP44

AHVSUP,
DVSUP, 
AVSUP

1300
1200
1000

960
960

mW
mW
mW
mW
mW

V

Idig

Input Voltage, all Digital Inputs

−0.3

V

SUP2

+0.3

V

I

Idig

Input Current, all Digital Pins

–

−20

+20

mA

1)

V

Iana

Input Voltage, all Analog Inputs

SCn_IN_s,

2)

MONO_IN

−0.3

V

SUP1

+0.3

V

I

Iana

Input Current, all Analog Inputs

SCn_IN_s,

2)

MONO_IN

−5

+5

mA

1)

I

Oana

Output Current, all SCART Outputs

SC1_OUT_s

2)

3)

, 

4)

3)

, 

4)

I

Oana

Output Current, all Analog Outputs 
except SCART Outputs

DACM_s

2)

3)

3)

I

Cana

Output Current, other pins 
connected to capacitors

CAPL_M,
AGNDC

3)

3)

1)

positive value means current flowing into the circuit

2)

“n” means “1” or “2”,     “s” means “L” or “R”

3)

The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground.

4)

Total chip power dissipation must not exceed absolute maximum rating.