Sharp MX-B381 / MX-B401 (serv.man9) Service Manual ▷ View online
MX-B381/B401 BLOCK DIAGRAM 1 – 3
3. PCU PWB
IC37
CPU
H8S/2373
IC47
or
IC48
RESET
IC
X1
Xtal
19.6608MHz
DC
Power
Supply
To
MFPC
Via
L
SU-Mother
To
LSU-Mother
FINISHER
DESK
Optional
IC29
EEPROM
(64kbit)
FLASH
ROM
IC39
SRAM
(1Mbit)
IC11
PMC
ASIC
Load
Control
O
utput
Coin-vendor
(Optional)
Sensor
Input
CPED1
/
MPED
/
M
PLD1
/
T
FD2
/
1
TNFD
Motor
L
ock
Detect
FAN_LD1/2
/
DVM_BK_LD
Fuser
T
hermistor
o
pen
d
etect
(THOPEN_MAIN)/
T
HOPEN_MAIN_LOW
/
THOPEN_MAIN_SUB
CRU
initial
detect
2TCCRU_in
/
F
UCRU_in
TNCRU_K
Fuser
unit
HL
control
HL_MAIN/HL_LOW/HL_E
HV
MC
/
T
C
DC
Motor
Control
DV
Motor
B
K(DVM_K)
Fuser
M
otor
(FUM)
FAN
Motor
Control
PS
FAN
(PSFM)
/
Procon
FAN
1
(PROFM1)
/
Procon
FAN
2
(PROFM2)
/
PoutFAN
(POFM)
/
Fuser
F
AN
(FUFM)/
LSU
F
AN
(LSUFM)
Drum
Lamp
(DL_K)
IC49
/
IC50
/
IC51
MUX
HC151x3
Sensor
Input
PPD2
Motor
Lock
Detect
FAN_LD4
Fuser
Thermistor
open
detect
THOPEN_EX1
Stepping
Motor
c
ontrol
Pout
Motor(POM)
/
Paper
F
eed
M
otor
(CPFM)
/
Resist
Motor(RRM)
Load
c
ontrol
Output
MPFS
/
C
PUC1
/
1
TURC_1
/
CPFC
/
A
DUC1
/
2
TURC
/
H
LPCS
/
DVCRU_K
Sensor
Input
CPFD1
/
PPD1
/
DHPD_K
/
POD2
/
DSW_F
/
D
SW_R
/
CLUD1
/
CSPD1
CRU
initial
detect
DRCRU_K_in
Synchronous
Motor
Toner
M
otor
(TNM_K)
DC
Motor
Lift
U
p
M
otor
(CLUM)
Analog
Input
Fuser
Thermistor(TH_MAIN/LOW/SUB/EX1/EX2)
Toner
C
ont.
sensor(TCS_K)
Process
C
ont.BK(REGS_R)
IC44
Spread
Spectrum
CRUM
CRUM_K
FW
UART
UART
UART
UART
I2C
B
us
AddressBus[20:0]
DATABus[15:0]
CLOCK
I2C
B
us
3-wired
PWM
Not
Mount
CLOCK
Load
c
ontrol
Output
FUCRU
FAN
Motor
Control
HDD
F
AN
(HDDFM)
IC34
CPLD
I2C
B
us
IC26
Analog
MUX
Write-Protect
IC23
D/A
C
onv
(TCS/REGS
cont)
Sensor
Input
CSS11-13
/
POD1
/
APPD1
/APPD2
/
1
TUD_K
/
1TUD_CL
Motor
Lock
D
etect
FUM_LD
/
FAN_LD3
/
F
AN_LD8
Fuser
Thermistor
open
detect
(THOPEN_MAIN_CS)
/
THOPEN_MAIN_EX2
CRU
initial
detect
DVCRU_K_in
/
D
RSET
TNCRU_K
HV
error
d
etect
PTC_ERR
/
M
C_BK_ERR
Drum
Lamp
open
detect
DLOPEN_K
Sensor
Input
COIN
VENDOR
(Optional)
CV_CLCOPY
/
CV_COPY
Analog
Input
Temp/Hum
sensor(TH_M/HUD_M)
LSU
T
hermistor(TH1_LSU)
DV
detector(DVTYP_K)
Multi-bypass
tray
w
idth
s
ensor(MPWD)
MX-B381/B401 BLOCK DIAGRAM 1 – 4
4. SCANNER CONTROL PWB
SCNcnt
Scanner
16
clk
RGB
32bit bus
mother
MFP
CLK 13.769MHz
CS3
CLK
SDIO
CTRL_A12V
SCLK
CTRL_A5V
/SEN
CTRL_A3.3V
CS4
/RESET
MHPS
MHPS
Mortor
RSPF UN
NRTS_SCN
CS2
CS0
NCTS_SCN
RXD_SCN
TXD_SCN
NRES_MFPC_SCN
RXD_SCN
TXD_SCN
NRES_MFPC_SCN
uart, others
RES_SCN
NPOF_SCN
NPOF_SCN
CS5
NFWP_SCN
LVDS PWB
/YL(Y1)
XH(X1)
YH(Y2)
/XL(X2)
XH(X1)
YH(Y2)
/XL(X2)
LCD detection
Touch panel
Touch panel
PNL_SEL0
PNL_SEL1
PNL_SEL1
CN_CHK_OUT
PNL_SEL2
PNL_SEL3
PNL_SEL3
PNL_SEL3
PNL_SEL0
PNL_SEL1
PNL_SEL2
PNL_SEL0
PNL_SEL1
PNL_SEL2
LCD_FPDCLK
CCFT
nLCD_DISP
LCD_A0+/-
LCD_A1+/-
LCD_A2+/-
LCD_A3+/-
LCD_CLK_+/-
LCD_A1+/-
LCD_A2+/-
LCD_A3+/-
LCD_CLK_+/-
KEY SCAN
nLCD_DISP
KEY PWB
/KEYIN
NINFO_LED
NPWRSW
POW_LED
NPWRSW
POW_LED
WU_LED
5V2
NWU_KEY
NINFO_LED
NPWRSW
POW_LED
WU_LED
NWU_KEY
5V2
NPWRSW
POW_LED
WU_LED
NWU_KEY
5V2
/BZR
FPD Link
DS90FC218A
SCN
ASIC
(Medusa)
LVDS IC
V385
CPU
H8S/2373
E2PROM
IO ASIC
SRAM
F-ROM
(DIMM)
IPD
KEY CON
MOTORDRIVER
L6219
12V/5V/3V
line buf
64Mbit x 2
12V
CLK27.53MHz
SS
M.M
TP
Rx
28bit
28bit
Rx
28bit
28bit
Tx
28bit
28bit
BUSBUF
powdown
powdown
3.3V
1.2V
INV PWB
LCD
FFC
CPLD
CN
AFE
LM98714
CCD
CL
HP sensor
1.5V
3.3V
1.2V
3.3V
DCDC-C
17V - 24V
CN
SS
LV047
FFC
MOTORDRIVER
L6219
244
MX-B381/B401 BLOCK DIAGRAM 1 – 5
5. LSU MOTHER PWB
LSU_ASIC
(Racoon)
MFP
BD
(BD/
TH)
Horizontal
Scan
/Vertical Scan
Timing Control
Motor Control
PCU
S/S
ECLK
HSYNC
LVDS/Driver
ECLK
HSYNC
VSYNC _K
VIDEO I/ F CK
HSYNC
ECLK
HSYNC
VSYNC
8
SYSCLK
PCU I/F
Register
etc...
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
JOBEND_INT
Synchronous Serial
communication
Thermistor Output
OSC
(System CK)
AMP
Reset
IC
Reset Input
Reset
35 : 5
ID[0:0]
Channel A: K1
Channel B: K2
Channel C:
Channel D:
LD
Polygon
Motor
Control
PGM_CK
PGM_START
(PGM_BRAKE)
PGM_LOCK
Polygon
Motor
FAN
Control
O. C.
O.C.
Serial
D/A
Serial I/F
DA_CLK
DA_DT
DA_LD
DA_LD
Vref K1, K2
Serial
D/A I/F
LD Control
LD Control
(APC
/ENB)
nSH K1,K2
LD _ENB K
LD5V
LDERR K
3
3
2
2
VIDEOIF_ACT
DT_K1+-
2
DT_K2+-
2
LD _CHK 1/2/ 3/4
4
BD
OSC
(CK C)
OSC
(CK M)
OSC
(CK A)
OSCCLK_C
OSCCLK_M
OSCCLK_A
CLK_C_EN
CLK_M_EN
CLK_A_EN
CLK_C_EN
CLK_M_EN
CLK_A_EN
Thermistor
4
PIC
PIC16F882
MFP
SCN
cnt
DCPS
LVDS
(OPE)
Reset
IC
Reset Input
Reset
UART
O.C
.
POF_MFP
POF_SCN
POF
O.C.
DCCNT1
O.C.
DCCNT2
UART
UART
LCD_DATA0-3 +-
/LCD_CLK+-
10
SCN_DATA0-3 +-
/SCN_CLK+-
10
LCD_DISP
USB Port
(Front)
USB
SW
O. C.
POW_LED
O. C.
WU_LED
PWR_KEY
WU_KEY
INFO_LED
O.C.
WU_FAX
LCDCLK
33.26MHz
LCD_CLKIN
PICVPPON
OSC
(System CK)
O. C.
TXD_PIC/RXD_PIC
REQ_PIC/REQ_PIC_INT/CLR_PIC
TXD_SCN/RXD_SCN/CTS_SCN/RTS_SCN/RES_SCN
LCD_SEL0-3
TXD _PCU
RXD_PCU
CTS _PCU
RXD_PCU
CTS _PCU
RTS _PCU
RES _PCU
RES _PCU
FPD-LINK/Receiver
MX-B381/B401 BLOCK DIAGRAM 1 – 6
6. SERIAL COMMUNICATION
MFPC
HDD
ASIC
PMC
G
A
uPD65946GJ
CPU
H8S/23
73
TxD_DSK
RxD_DSK
TxD_F
IN
RxD_F
IN
O.
C
.
O.
C
.
O.
C
.
O.
C
.
CPLD
EPM240T
100C5
O.
C
.
O.
C
.
O.
C
.
O.
C
.
CPU
M30843F
W
GP
Schmit
Inv.
O.C
.
O.C
.
O.C
.
CP
U
H8/
3684
DTR_
FIN
DSR_FIN
DTR_
DS
K
DSR_DS
K
PCU
IN
DESK
(Optional)
NER
FIN
ISHER
䋨Optional)
Schmit
Inv.
O.C
.
O.C
.
O.C
.
A[3
:0]
D[
15:
8]
Schmit
In
v.
Schmit
In
v.
Schmit
In
v.
SCK_LSU
RSV_DAT
TRANS_DAT
Schmit
Inv.
Schmit
Inv.
Schmit
Inv.
LSU
A
SIC
O.
C
.
nPCU_RxD
Schmit
In
v.
nPCU_TxD
O.
C
.
P
C
U_DSR
Schmit
In
v.
PCU_DTR
Schm
it
Inv.
O.
C.
Schm
it
Inv.
O.
C.
O.
C
O.
C.
Sc
hm
it
In
v.
O.
C.
nT
xD
_S
CN
nRxD_SCN
RTS_SCN
CPU
H8S/237
3
Sc
hm
it
In
v.
Schmit
Inv.
O.
C
Sc
hm
it
In
v.
C
TS_
SC
N
TxD0
I/O
ASIC
μPD65892GC
O.
C
O.
C.
Schm
it
Inv.
O.
C.
DTR_
FAX(D)
DS
R_
FAX
(D)
DTR_
FAX(CS)
Sc
hm
it
In
v.
Sc
hm
it
In
v.
O.
C
Schm
it
Inv.
DSR_FAX
(CS)
P.D.
P.U.
P.
D.
P.U.
P.
D.
P.
U.
P.U.
P.
D
.
P.D.
P.
U.
P.U.
P.
U.
P.U.
P.U.
P.U.
P.
U.
P.U.
P.U.
P.U.
P.U.
P.
U
.
P.U.
P.U.
P.
U
.
P.U.
P.U.
P.
U
.
P.U.
P.U.
P.
U
.
P.
D
.
P.D.
P.
U
.
P.
U
.
P.D.
P.U.
P.U.
P.U.
P.D.
P.D.
P.U.
P.D.
A[
4:
0]
D[
15:
8]
P.D.
P.U.
P.
U
.
P.D.
P.D.
P.U.
P.
U
.
P.D.
TxD_F
A
X
(D)
RxD_F
A
X
(D)
TxD_F
A
X
(CS)
Rx
D
_F
A
X(C
S
)
LVDS
RxD0
I/O
port
I/O
port
TxD1
RxD1
SCK1
Tx
D2
RxD2
TxD3
RxD3
RxD
Tx
D
SCK
RxD
Tx
D
I/O
I/O
RxD
Tx
D
I/O
I/O
RxD[1]
TxD[
1]
CTS[
1]
RT
S
[1]
RxD[
2]
Tx
D[2
]
CTS[2
]
RTS[2
]
Rx
D
[3
]
Tx
D[
3]
CTS[
3]
RTS[
3]
TxD[
4]
Rx
D
[4
]
CTS[
4]
RTS[
4]
PIC
PI
C16F882
TxD[
P
IC]
RxD[PI
C]
O.
C.
Sc
hm
it
In
v.
P.U.
P.D.
nT
xD_PIC
O.
C
Schmit
Inv.
nRxD_PIC
P.
U
.
CL
R[PIC
]
O.
C.
O.
C
P.U.
CLR_
P
IC
REQ
[PIC
]
Schmit
Inv.
RE
Q
_PIC
O.
C
P.
U
.
LSU-MOTHER
SCN
C
nt
MFPC
FAX
New ASIC
Tx
D_FAX(D)+
Tx
D_FAX(D)-
RxD_F
A
X(D)+
RxD_F
A
X
(D)-
Tx
D_FAX(CS)
+
Tx
D_FAX(CS)
-
RxD_FA
X
(CS)+
RxD_FA
X(CS)-
RxD
Tx
D
PIC
CPU
SH7706
TxD
RxD
P.U.
A[9:0
]
D[15:8]
Tx
D[PI
C]
Rx
D
[PIC]
CLR[PIC]
REQ[
P
IC]
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