Sharp MX-4100N / MX-4101N / MX-5000N / MX-5001N (serv.man18) Service Manual ▷ View online
MX-4101N ELECTRICAL SECTION 10 – 5
D. Scanner control PWB
DSPF model
RGB
AFE_CS
Two serial systems
AD_CLK
AFE_CSTG
SH, φ1, others
motor
sensors
24V
12V
5V
3.3V
12V
5V
3.3V
Power supply
To CPU
RGB DATA
Image data
SCNcnt
AFE_CS
16
16
AD_CLK
clk
RGB
AFE_CSTG
32bit bus
mother
SH, φ1, others
Two serial systems
Image data
CS3
CTRL_A10V
CTRL_A5V
CTRL_A3.3V
CTRL_A5V
CTRL_A3.3V
CS4
CS2
CS0
RSPF UN
RSPF model
RSPF model
SEL_A/B/C
Sensors
Sensors
CS5
PNL_SEL0
PNL_SEL1
PNL_SEL2
PNL_SEL1
PNL_SEL2
LCD_SKT
PNL_SEL3
LCDs detection
Touch panel
Touch panel
LCDs detection
CCFT_CPU
/CCFT
nLCD_DISP
(ON/OFF)
(ON/OFF)
KEY PWB
PDSEL0
PDSEL1
PDSEL2
PD
PDSEL1
PDSEL2
PD
5V2
NINFO_LED
NPWRSW
POW_LED
WU_LED
NWU_KEY
5V2
NPWRSW
POW_LED
WU_LED
NWU_KEY
5V2
/BZR
CCD-R
(DSPF side)
DSPFcnt
(Machine side)
CCD-F
SCN
ASIC
line buf
(8Mx16bit)
LVDS IC Tx
28bit
CPU
H8S/2373
E2PROM
IO ASIC
SRAM
F-ROM
(DIMM)
(DIMM)
Copy Lamp
KEY CON
3line color CCD
TCD2716ADG
BUFFER
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
AFE
Timing
generator
MOTOR
DRIVER
DRIVER
Oscillator
BUFFER
5V/.33V
3.3V
10V
10V/5V/3V
1.8V
line buf
(8Mx16bit)
12
5V
12
10V
5
3.3V
Oscillator
SS
MOTOR
DRIVER
DRIVER
Mirror
.Motor
.Motor
HC151
HC151
Touch panel
BUSBUF
powdown
powdown
1.5V
3.3VPD
3.3VPD
1.2V
Buzzer
LED drive circuit
INV PWB
8.5 inch
LCD
Vcc REG
LED matrix
LVDS PWB (8.5 inch TFT)
or
LVDS PWB (8.1 inch mono)
or
LVDS PWB (8.1 inch mono)
IPD/IDOCC
MHP sensor
ORS LED
F-ROM
(for Shading DATA storage)
SCN
ASIC
(Medusa)
LVDS IC Tx
28bit
CPU
H8S/2373
SRAM
F-ROM
(DIMM)
Page Memory
256MBYTE(256Mbitx8)
CL
DRIVER
PWB
3line color CCD
TCD2716ADG
BUFFER
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
Tr
AFE
Timing
generator
Oscillator
BUFFER
5V/3.3V
3.3V
10V
1.8V
LVDS IC Rx
28bit
DRIVER
(74VHCT
244)
10V/5V/3V
Original size sensor
BUS
SW
Rx
28bit
28bit
/KEYIN
Rx FPD Link
35bit
Rx FPD Link
35bit
uart, others
Communication, others
MX-4101N ELECTRICAL SECTION 10 – 6
E. LSU PWB
LSU_ASIC
CHIP-2
LSU_ASIC
CHIP-1
MFP
Thermistor
Main Scan/
Sub scan
timing control
Motor control
PCU
S/S
ECKL
HSYNC
L
VDS/Dri
ver
ECLK
HSYNC
VSYNC_M/Y
Image transfer CK
HSYNC
8
ECLK
HSYNC
VSYNC
8
ASIC
CHIP-2
ASIC
CHIP-2
SYSCLK
PCU I/F
Register etc...
ASIC
CHIP-2
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
ASIC
CHIP-2
JOBEND_INT
Interruption output
Clock synchronous serial communication
Thermistor output
Oscillator
(System CK)
PCU_TRG
Print trigger input
AMP
Reset input
Hardware reset
35:5
35:5
ID[0:0]
Channel A: K1 circuit
Channel B: K2 circuit
Channel C: C1 circuit
Channel D: C2 circuit
PCU I/F
Register etc...
ID[0:1]
I2C
ROM
I2C
ROM
I2C bus
ASIC
CHIP-2
Hardware reset
ASIC
CHIP-2
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronous serial communication
Interruption output
System CK
ECLK
HSYNC
8
8
35:5
35:5
F
PD
-L
IN
K
/R
eci
ver
Print trigger chain
LD
BD
Polygon
control
PGM_CK
PGM_START
(PGM_BREAK)
PGM_LOCK
Polygon
motor
LSU
FAN
FAN
FAN control
FAN_PWM
FANSTABLE
I2C BUS
O.C.
O.C.
O.C.
Serial
D/A
Serial transfer
DA_CLK
DA_DT
DA_LD
DA_LD
Vref YMCK x2
Serial
D/A I/F
LD control
LD control
(APC etc...)
nSHMY x2
LD_ENB MY
O.C.
LDERR YMCK
DT_M1+-
3
3
8
4
2
2
VIDEOIF_ACT
DT_M2+-
2
DT_Y1+-
2
DT_Y2+-
2
F
PD
-L
IN
K
/R
eci
ver
DT_K1+-
2
DT_K2+-
2
DT_C1+-
2
DT_C2+-
2
Motor control
Polygon
control
FAN control
Serial
D/A I/F
LD control
LD control
(APC etc...)
LD_CHK 1/2/3/4
4
ASIC
CHIP-2
BD
AKM_SCK
AKM_SDT
AKM_SDT
2
O.C.
nSH KC x2
LD_ENB KC
LD5V
4
2
AKM_SDCLK
BD
AKM_CS_CMYK
4
AKM LDD serial communication
nSHB MY x2
4
AKM_APCSEL_CMYK
nSHB MY x2
nSHB KC x2
nSHB KC x2
Reserve circuit for LDD made by AKM
nSHB KC x2
Oscillator
(Color CK)
Oscillator
(Monochrome CK)
Oscillator
(Heavy paper CK)
OSCCLK_C
OSCCLK_M
OSCCLK_A
CLK_C_EN
CLK_M_EN
CLK_A_EN
CLK_C_EN
CLK_M_EN
CLK_A_EN
TH
AKM_RESET_LDD
Channel A: M1 circuit
Channel B: M2 circuit
Channel C: Y1 circuit
Channel D: Y2 circuit
PIC
3
ASIC
CHIP-2
VSYNC_K/C
VSYNC_K/C
4
LD5V
Reset IC
Main Scan/
Sub scan
timing control
MX-4101N ELECTRICAL SECTION 10 – 7
F. Serial communication
C
P
U
H
8S/2
3
7
3
TxD
_
DS
K
R
xD
_
DS
K
TxD
_F
IN
R
xD
_F
IN
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
I/
OA
SI
C
µPD
6
5
8
9
2
GC-
10
3
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
C
P
U
M3
08
43FWG
P
Sc
hm
it
In
v.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
C
P
U
H
8/
3
6
8
4
C
P
U
H
8/
3
6
8
7
DT
R_F
IN
DS
R_F
IN
DT
R_
DS
K
DS
R_
DS
K
DT
R_LCC
TxD
_LCC
R
xD
_LCC
DS
R_LCC
P
CU
F
INIS
H
E
R
(O
ptional
)
DES
K
(O
ptional
)
LCC
(O
ptional
)
)
Sc
hm
it
In
v.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
O
.C
.
A[
4:0
]
D
[1
5:8
]
Sc
hm
it
In
v.
Sc
hm
it
In
v.
Sc
hm
it
In
v.
S
CK_L
S
U
R
SV
_
D
A
T
T
RA
NS
_
D
A
T
Sc
hm
it
In
v.
Sc
hm
it
In
v.
Sc
hm
it
In
v.
L
S
UA
SI
C
O
.C
.
nP
CU_R
xD
Sc
hm
it
In
v.
nP
CU_
TxD
O
.C
.
P
CU_
DS
R
Sc
hm
it
In
v.
P
CU_
DT
R
Sc
hm
it
In
v.
O
.C
.
Sc
hm
it
In
v.
O
.C
.
MF
P
C
I/
FA
SI
C
O
.C
O
.C
.
Sc
hm
it
In
v.
O
.C
.
nT
xD
_S
C
N
nR
xD
_S
C
N
R
T
S
_S
C
N
C
P
U
H
8S/2
37
3
Sc
hm
it
In
v.
Sc
hm
it
In
v.
O
.C
Sc
hm
it
In
v.
C
TS
_S
C
N
S
chmi
t
Tx
D
0
Sc
hm
it
O
.C
.
O
.C
Sc
hm
it
In
v.
Sc
hm
it
In
v.
O
.C
.
O
.C
.
TxD_S
CAN
RxD
_S
CAN
I/
OA
SI
C
µPD
6
5
8
9
2
GC
O
.C
O
.C
.
Sc
hm
it
In
v.
O
.C
.
DT
R_FA
X
(D
)
DS
R_FA
X
(D
)
DT
R_FA
X
(C
S
)
Sc
hm
it
In
v.
Sc
hm
it
In
v.
O
.C
Sc
hm
it
In
v.
DS
R_FA
X
(C
S
)
P.
D
.
P.
U
.
P.
D
.
P.
U
.
P.
D
.
P.
U
.
P.
U
.
P.
D
.
P.
D
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
U
.
P.
D
.
P.
D
.
P.
U
.
P.
U
.
P.
D
.
P.
U
.
P.
U
.
P.
U
.
P.
D
.
P.
D
.
P.
U
.
P.
D
.
P.D
.
P.U
.
P.U
.
P.D
.
P.U
.
P.D
.
P.U
.
P.D
.
A[
4:0
]
D
[1
5:8
]
P.
D
.
P.
U
.
P.
U
.
P.
D
.
P.
D
.
P.
U
.
P.
U
.
P.
D
.
TxD
_FA
X
(D
)
R
xD
_FA
X
(D
)
TxD
_FA
X
(C
S
)
R
xD
_FA
X
(C
S
)
LVD
S
R
xD
0
I/O
port
I/O
port
Tx
D
1
R
xD
1
S
CK
1
Tx
D
2
R
xD
2
Tx
D
3
R
xD
3
Tx
D
4
R
xD
4
R
xD
Tx
D
S
CK
R
xD
TxD
I/
O
I/
O
R
xD
TxD
I/
O
I/
O
R
xD
TxD
I/
O
I/
O
R
xD
[1
]
Tx
D
[1
]
C
TS
[1
]
R
TS
[1
]
R
xD
[2
]
Tx
D
[2
]
C
TS
[2
]
R
TS
[2
]
R
xD
[3
]
Tx
D
[3
]
C
TS
[3
]
R
TS
[3
]
Tx
D
[4
]
R
xD
[4
]
C
TS
[4
]
R
TS
[4
]
PI
C
Tx
D
[PI
C]
R
xD
[PI
C]
O
.C
.
Sc
hm
it
In
v.
P.
U
.
P.
D
.
nT
xD
_PI
C
O
.C
Sc
hm
it
In
v.
nR
xD
_PI
C
P.
U
.
CL
R
[PI
C]
O
.C
.
O
.C
P.
U
.
CL
R
_PI
C
R
E
Q[
PI
C]
Sc
hm
it
In
v.
R
E
Q_
PI
C
O
.C
P.
U
.
L
S
U
DSP
FC
nt
(for
DSP
F
model
)
S
C
N
C
nt
M
ot
he
r
MF
P
C
1st
FAX
(for
FG
M
odel
)
RxD
TxD
DS
R_
S
CA
N
DT
R_
S
CA
N
I/O
I/O
Ne
w
A
SI
C
Tx
D
_F
A
X
(D
)+
Tx
D
_F
A
X
(D
)-
R
xD
_F
A
X
(D
)+
R
xD
_F
A
X
(D
)-
Tx
D
_F
A
X
(C
S
)+
Tx
D
_F
A
X
(C
S
)-
R
xD
_F
A
X
(C
S
)+
R
xD
_F
A
X
(C
S
)-
C
P
U
S
H7
70
6
PI
C
Tx
D
R
xD
2nd
FAX
(same
as
1st
)
(O
ptional
)
P.
U
.
.
In
v.I
nv
.
C
P
U
H
8S/2
373
TxD
RxD
R
xD
TxD
MX-4101N ELECTRICAL SECTION 10 – 8
G. AC power line diagram (120V)
HLOU
T
_UM
INT2
4
V1
HLOU
T
_
E
X
/HL_
P
R
HLOU
T
_U
S
2
4
V
3
WH_C
NT
HLOU
T
_LM
L
N
1
5A
/2
5
0V
2
6
R
Y
1
6
2
G
T1
G
ND
1
G
4
4
G
ND
T1
1
T2
dra
w
er
TD1
SS
R
1S
S
R
2
HL_UM
FU
SIN
GU
NIT
6
2
G
ND
G
4
1
SS
R3
T2
T1
T2
MA
IN
P
OW
E
R
S
W
T2.0
AH
/2
5
0V
WH-L
WH-
N
F3
N/
F
AC
IN
TD2
TD
3
1
5A
/2
5
0V
T
5AH
/2
5
0V
T8
AH
/2
5
0V
T2
AH
/2
5
0V
D
C
P
OW
E
R
S
U
PP
L
Y
Volta
g
e
G
eneration
+5
Vo
+5
V
L
AC
P
W
B
no
-mountin
g
no
-mountin
g
no
-
mountin
g
HL
P
W
B
FW
G
eneratin
g
C
ircuit
Volta
g
e
G
eneration
+
2
4
V1
+
2
4
V2
+
2
4
V
3
+
2
4
V
4
+
2
4
V
5
+
12V
+5
VN
+3
.3
V
WH-L
WH-
N
N
C
N
O
10
W
LCC
10
W
DES
K
MA
IN
U
NIT
10
W
MA
IN
U
NIT
S
C
N
S
C
Nu
n
it
O
PTI
O
N
7W
DES
K
LCC
WARM
H
E
A
TE
R
SET
:
O
PTI
O
N
WH
P
W
B
O
PTI
O
N
10
W
1
4W
L
S
U
L
S
U
O
PTI
O
N
CC
D
TD
4
6
2
G
ND
G
4
1
SS
R4
T1
T2
HL_LM
TS
_
E
X
2
T
H
E
RMO
ST
A
T
TS
_LM
T
H
E
RMO
ST
A
T
HL_
E
X
1
HL_
E
X
2
T
H
E
RMO
ST
A
TT
S
_
E
X
1
T
H
E
RMO
ST
A
TT
S
_MA
IN
R
Y
1
R
R
Y
1
A3
WH-
S
W
V
R
1
V
R3
F
101
A
1
A
2
F
002
L
2
X
001
X
001
V
R
2
L
1
F
001
F
201
~
~
+
-
D20
4
F
1
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