Sharp DM-1500 (serv.man2) Service Manual ▷ View online
PIN No.
Signal name
IN/OUT
Connected to
Description
141
SOE0
OUT
SRAM (separation)
Read enable line to SRAM before area separation
142
SWE0
OUT
SRAM (separation)
Write enable line to SRAM before area separation
143
SCS0
OUT
SRAM (separation)
Chip select line to SRAM before area separation
144
SD00
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
145
SD01
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
146
5V
Power
147
SD02
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
148
SD03
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
149
GND
Power
150
SD04
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
151
SD05
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
152
SD06
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
153
SD07
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
154
SAD0
OUT
SRAM (separation)
Address line to SRAM before area separation
155
SAD1
OUT
SRAM (separation)
Address line to SRAM before area separation
156
SAD2
OUT
SRAM (separation)
Address line to SRAM before area separation
157
SAD3
OUT
SRAM (separation)
Address line to SRAM before area separation
158
SAD4
OUT
SRAM (separation)
Address line to SRAM before area separation
159
SAD5
OUT
SRAM (separation)
Address line to SRAM before area separation
160
SAD6
OUT
SRAM (separation)
Address line to SRAM before area separation
161
SAD7
OUT
SRAM (separation)
Address line to SRAM before area separation
162
GND
Power
163
SAD8
OUT
SRAM (separation)
Address line to SRAM before area separation
164
SAD9
OUT
SRAM (separation)
Address line to SRAM before area separation
165
SAD10
OUT
SRAM (separation)
Address line to SRAM before area separation
166
SAD11
OUT
SRAM (separation)
Address line to SRAM before area separation
167
SAD12
OUT
SRAM (separation)
Address line to SRAM before area separation
168
SAD13
OUT
SRAM (separation)
Address line to SRAM before area separation
169
/f1
OUT
CCD PWB
CCD drive signal transfer clock (First phase)
170
/f2
OUT
CCD PWB
CCD drive signal transfer clock (Second phase)
171
/SH
OUT
CCD PWB
CCD drive signal shift pulse
172
5V
Power
173
RS
OUT
CCD PWB
CCD drive signal reset pulse
174
SP
OUT
CCD PWB
CCD drive signal sampling hold pulse
175
GND
Power
176
CP
OUT
CCD PWB
A/D conversion IC latch clock
177
BCLK
OUT
CCD PWB
CCD shield output latch signal
178
IDIN0
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
179
IDIN1
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
180
IDIN2
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
181
IDIN3
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
182
IDIN4
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
183
IDIN5
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
184
IDIN6
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
DM-1505
11 – 8
PIN No.
Signal name
IN/OUT
Connected to
Description
185
5V
Power
186
IDIN7
IN
CCD PWB (AD
conversion)
conversion)
Image scan data (after 8bit A/D conversion)
187
/SDCLK
OUT
CHECK
Effective image area signal
188
GND
Power
189
SFCLK
IN
Transmitter
CCD drive clock (48MHz), Also used as an internal clock.
190
TEST port 0
IN
AUTO SCAN TEST
High: Normal Low: Test
191
/SYNC
IN
LSU
Horizontal synchronization signal (HSYNC) from LSU
192
/LD
OUT
LSU
Laser drive signal
193
/LEND
OUT
LSU
Laser APC signal
194
USB-EN
OUT
GDI/USB PWB
USB port enable signal
195
1284-EN
OUT
GDI/USB PWB
1284 port enable signal
196
PORTOUT26
OUT
(Not used)
197
3.3V
Power
198
PORTOUT25
OUT
(Not used)
199
PORTOUT24
OUT
(Not used)
200
GND
Power
201
SGS
OUT
Tr array IC
SPF gate solenoid
202
SRRC
OUT
Tr array IC
SPF resist roller solenoid
203
SPUS
OUT
Tr array IC
SPF PU solenoid
204
/READY
OUT
Reserved
205
OP-LATCH
OUT
Tr array IC
Latch signal for operation circuit. Data latch at LOW.
206
MRPS2
OUT
Tr array IC
Mirror speed control signal. Mirror speed 2 at LOW.
207
MRPS1
OUT
Tr array IC
Mirror speed control signal. Mirror speed 1 at LOW.
208
SPFS
OUT
Tr array IC
SPF paper feed solenoid
209
SMSEL
OUT
Tr array IC
SPF motor/Mirror motor select signal
210
3.3V
Power
211
TC
OUT
Tr array IC
Transfer charger control signal. ON at HIGH.
212
GRIDL
OUT
Tr array IC
Main charger grid control signal. ON at HIGH.
213
GND
Power
214
MC
OUT
Tr array IC
Main charger control signal. ON at HIGH.
215
BIASL
OUT
Tr array IC
DV bias voltage control signal. ON at HIGH.
216
BIASH
OUT
Tr array IC
DV bias voltage control signal. ON at HIGH.
217
BIAS
OUT
Tr array IC
DV bias output control signal. ON at HIGH.
218
CL
OUT
Tr array IC
Copy lamp control signal. ON at HIGH.
219
VFMCNT
OUT
Tr array IC
Ventilation fan rotating speed control signal. Low speed at HIGH, high
speed at LOW.
speed at LOW.
220
VFM
OUT
Tr array IC
Ventilation fan control signal. Fan ON at HIGH.
221
LDEN
OUT
Tr array IC
Laser circuit control signal. Laser circuit ON at HIGH.
222
PMD
OUT
Tr array IC
Polygon motor control signal. Polygon motor ON at HIGH.
223
5V
Power
224
MM
OUT
Tr array IC
Main motor control signal. Main motor ON at HIGH.
225
MPFS
OUT
Tr array IC
Manual paper feed solenoid control signal. Multi paper feed ON at
HIGH.
HIGH.
226
GND
Power
227
CPFS2
OUT
Tr array IC
Second cassette paper feed solenoid control signal. Second cassette
paper feed at HIGH.
paper feed at HIGH.
228
CPFS1
OUT
Tr array IC
Cassette paper feed solenoid control signal. One-stage cassette paper
feed at HIGH.
feed at HIGH.
229
TM
OUT
Tr array IC
Toner motor drive output (+)
DM-1505
11 – 9
PIN No.
Signal name
IN/OUT
Connected to
Description
230
TM_
OUT
Tr array IC
Toner motor drive output (–)
231
CPUD15
IN/OUT
CPU
CPU data bus
232
CPUD14
IN/OUT
CPU
CPU data bus
233
CPUD13
IN/OUT
CPU
CPU data bus
234
CPUD12
IN/OUT
CPU
CPU data bus
235
CPUD11
IN/OUT
CPU
CPU data bus
236
5V
Power
237
CPUD10
IN/OUT
CPU
CPU data bus
238
CPUD9
IN/OUT
CPU
CPU data bus
239
GND
Power
240
CPUD8
IN/OUT
CPU
CPU data bus
241
CPUD7
IN/OUT
CPU
CPU data bus
242
CPUD6
IN/OUT
CPU
CPU data bus
243
CPUD5
IN/OUT
CPU
CPU data bus
244
CPUD4
IN/OUT
CPU
CPU data bus
245
CPUD3
IN/OUT
CPU
CPU data bus
246
CPUD2
IN/OUT
CPU
CPU data bus
247
CPUD1
IN/OUT
CPU
CPU data bus
248
CPUD0
IN/OUT
CPU
CPU data bus
249
3.3V
Power
250
/CPUWR
IN
CPU
CPU write signal
251
/CPURD
IN
CPU
CPU read signal
252
GND
Power
253
CPUCLK
IN
CPU
CPU system clock
254
GND
Power
255
TEST PORT1
IN
AUTO SCAN TEST
High: Normal Low: Test
256
/SCANST
IN
CPU (I/O)
Scanner process start signal
∗ The signals which are hatched are added or revised to or from AL-1000.
(3) Expanded PWB interface section
The MCU PWB and the expanded PWB are connected by CN5 connector to make serial communication (UART).
The FAX PWB uses signals in Table A, and the PCL PWB uses signals in Table B.
Recognition of FAX PWB or PCL PWB:
If /FREADY is LOW, the FAX PWB expansion is recognized.
If /PREADY is LOW, the PCL PWB expansion is recognized.
The FAX PWB uses signals in Table A, and the PCL PWB uses signals in Table B.
Recognition of FAX PWB or PCL PWB:
If /FREADY is LOW, the FAX PWB expansion is recognized.
If /PREADY is LOW, the PCL PWB expansion is recognized.
OUTD6
OUTD1
OUTD13
/PCLPRD
/F-RESET
/FAXCS
OUTD8
OUTD11
/PCLACK
/PAGE
OUTD10
OUTD5
/PCLREQ
OUTD0
/FAXPRD
/PREADY
OUTD3
/FREADY
OUTD12
OUTD15
OUTD2
/FAXACK
OUTD14
OUTD9
/HSYNC
/FAXREQ
/PCLCS
OUTD4
OUTD7
FTXD
/FCTS
FRXD
/SCANST
/READY
/POFF
/PRSTART
/FRTS
12V
3.3V
5V
0.1u
C137
0.1u
C135
0.1u
C134
TX25-60P-23ST-H1
CN5
SBO-02SAN
L1
18p
C141
0.1u
C118
47u 25V
C3
0.1u
C119
47u 16V
C5
0.1u
C117
SBO-02SAN
L2
SBO-02SAN
L3
47u 16V
C2
18p
C143
10J
R132
18p
C140
10J
R130
10J
R128
10J
R131
18p
C142
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
16
15
17
14
13
12
11
10
9
8
7
6
5
4
3
2
1
/FRTS
OUTD1
OUTD11
/FREADY
OUTD12
OUTD0
/FAXPRD
/PREADY
OUTD7
OUTD8
OUTD10
FRXD
/PCLCS
/FAXREQ
/FAXACK
F-RESET
/PCLREQ
/HSYNC
/PRLINE
/PCLACK
OUTD6
OUTD13
/FAXCS
/FCTS
FTXD
OUTD15
/POFF
OUTD4
/PCLPRD
OUTD3
OUTD9
/FPAGE
OUTD2
OUTD14
OUTD5
/SCLINE
/READY
(1-D2)
(5-E1)
(5-E1)
(5-E1)
(7-E2)
(1-D4)
(1-E1)
(1-C1)
(5-A3)
(7-E2)
(7-D1)
(7-E1)
(7-E1)
(7-E1)
(7-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E1)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
(5-E2)
PCL/FAX CN
DM-1505
11 – 10
Table A (Signals used in the FAX PWB)
PIN No.
(CN5)
Signal
name
IN/OUT
Descriptions
3
/SCLINE
OUT
Effective input image area
6
FTXD
OUT
Serial communication data
7
/FRTS
OUT
Serial reception ready
(Machine side)
(Machine side)
12
/F-RESET
OUT
Reset signal
13
/HSYNC
OUT
Horizontal sync signal
14
∼ 21,
44
∼ 51
OUTD1
∼
OUTD15
OUT
Data to the expanded PWB
24
/FAXREQ
OUT
Data transfer REQ signal
25
/FAXCS
IN
OUTD bus enable signal
33
/PRLINE
OUT
Effective print area
34
/FPAGE
IN
Page data READY
35
/FREADY
IN
FAX PWB recognition signal
36
/READY
OUT
READY signal on the
machine side
machine side
37
FRXD
IN
Serial communication data
38
/FCTS
IN
Serial reception READY
(FAX side)
(FAX side)
43
/POFF
OUT
Power OFF signal
54
/FAXPRD
IN
Video data from FAX PWB
55
/FAXACK
IN
Data transfer ACK signal
Table B (Signals used in PCL PWB)
PIN No.
(CN5)
Signal
name
IN/OUT
Descriptions
5
/PREADY
IN
PCL PWB recognition signal
6
FTXD
OUT
Serial communication data
7
/FRTS
OUT
Serial reception READY
(Machine side)
(Machine side)
12
/F-RESET
OUT
Reset signal
13
/HSYNC
OUT
Horizontal sync signal
34
/FPAGE
IN
Page data READY
36
/READY
OUT
READY signal on the
machine side
machine side
37
FRXD
IN
Serial communication data
38
/FCTS
IN
Serial reception READY
(PCL side)
(PCL side)
52
/PCLPRD
IN
Video data from PCL PWB
(4) 1284/USB circuit select control section
The GDI/USB PWB is connected to CN15 connector to control switch-
ing between IEEE1284 port and USB port.
If USB cable isn’t connected to the GDI/USB PWB, the /1284-EN signal
becomes LOW to allow the user of IEEE1284 port.
ing between IEEE1284 port and USB port.
If USB cable isn’t connected to the GDI/USB PWB, the /1284-EN signal
becomes LOW to allow the user of IEEE1284 port.
If USB cable is connected, the /USB-EN signal becomes LOW to allow
the use of USB port.
Since USB has priority, when USB cable is connected, it is selected.
That is, when USB cable is connected, IEEE1284 port (parallel port) is
disabled.
the use of USB port.
Since USB has priority, when USB cable is connected, it is selected.
That is, when USB cable is connected, IEEE1284 port (parallel port) is
disabled.
USB-IN
/1284-EN
USB-ON
/USB-EN
/GDI-IN
/ACK
PARAAD5
SLCT
PARAAD6
PARAAD7
/STB
PARAAD1
/REV
PARAAD3
PARAAD0
INIT
BUSY
/SLCTIN
/AUTOFD
PE
/FAULT
PARAAD2
PARAAD4
3.3V
5V
31FT-BT-VK-N
CN15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(5-A3)
(5-A3)
(1-B1)
(5-A3)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(2-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D3)
(5-D3)
(5-D2)
(5-D2)
(5-D2)
GDI/USB CN
DM-1505
11 – 11
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