Sharp AR-161 (serv.man15) Service Manual ▷ View online
2. MCU
(1) Block diagram (MCU)
(2) CPU (HD6412351IF)
a. pin/signal table
Pin No.
Pin name
Signal name
I/O
Function
Purpose
Descriptions
1
/CS1
/CS1
OUT
Area 1 chip select
SRAM chip select
L: Select
2
/CS0
/CS0
OUT
Area 0 chip select
Flash ROM chip select
L: Select
3
VSS
POW
Ground pin
4
VSS
POW
Ground pin
5
VCC
POW
Power pin
6
A0
A0
OUT
Address bus 0
System bus
7
A1
A1
OUT
Address bus 1
System bus
8
A2
A2
OUT
Address bus 2
System bus
9
A3
A3
OUT
Address bus 3
System bus
10
VSS
POW
Ground pin
11
A4
A4
OUT
Address bus 4
System bus
12
A5
A5
OUT
Address bus 5
System bus
13
A6
A6
OUT
Address bus 6
System bus
14
A7
A7
OUT
Address bus 7
System bus
15
A8
A8
OUT
Address bus 8
System bus
16
A9
A9
OUT
Address bus 9
System bus
17
A10
A10
OUT
Address bus 10
System bus
18
A11
A11
OUT
Address bus 11
System bus
19
VSS
POW
Ground pin
20
A12
A12
OUT
Address bus 12
System bus
21
A13
A13
OUT
Address bus 13
System bus
(Pin descriptions) IN: Input pin OUT: Output pin BIDIR: Bi-directional pin ODN: Open drain output pin TR1: 3-state output pin POW: Power pin
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Pin No.
Pin name
Signal name
I/O
Function
Purpose
Descriptions
22
A14
A14
OUT
Address bus 14
System bus
23
A15
A15
OUT
Address bus 15
System bus
24
A16
A16
OUT
Address bus 16
System bus
25
A17
A17
OUT
Address bus 17
System bus
26
A18
A18
OUT
Address bus 18
System bus
27
A19
A19
OUT
Address bus 19
System bus
28
VSS
POW
Ground pin
29
A20
A20
OUT
Address bus 20
System bus
30
/IRQ5
/SPFCOVER
IN
Interruption request 5
SPF cover sensor interruption
1: Cover close
31
/IRQ6
/OCCOVER
IN
Interruption request 6
OC cover sensor interruption
0: Cover close
32
/IRQ7
MHP
IN
Interruption request 7
Mirror home position sensor
interruption
interruption
1: Home position
33
/IRQ3
/SPFPAPER
IN
Interruption request 3
SPF paper pass sensor
interruption
interruption
0: Paper presence
34
/IRQ2
/CPUSYNC
IN
Interruption request 2
Horizontal sync signal
interruption
interruption
0: Effective
35
VSS
POW
Ground pin
36
VSS
POW
Ground pin
37
/IRQ1
/FW
IN
Interruption request 1
Zero cross interruption
0: Effective
38
/IRQ0
/LOOPINT
IN
Interruption request 0
Loop interruption
0: Effective
39
VCC
POW
Power pin
40
D0
D0
BIDIR
Data bus 0
System bus
41
D1
D1
BIDIR
Data bus 1
System bus
42
D2
D2
BIDIR
Data bus 2
System bus
43
D3
D3
BIDIR
Data bus 3
System bus
44
VSS
POW
Ground pin
45
D4
D4
BIDIR
Data bus 4
System bus
46
D5
D5
BIDIR
Data bus 5
System bus
47
D6
D6
BIDIR
Data bus 6
System bus
48
D7
D7
BIDIR
Data bus 7
System bus
49
D8
D8
BIDIR
Data bus 8
System bus
50
D9
D9
BIDIR
Data bus 9
System bus
51
D10
D10
BIDIR
Data bus 10
System bus
52
D11
D11
BIDIR
Data bus 11
System bus
53
VSS
POW
Ground pin
54
D12
D12
BIDIR
Data bus 12
System bus
55
D13
D13
BIDIR
Data bus 13
System bus
56
D14
D14
BIDIR
Data bus 14
System bus
57
D15
D15
BIDIR
Data bus 15
System bus
58
VCC
POW
Power pin
59
P30
—
OUT
General port 30
Reservation
L: Level fixing output
60
TXD1
TXD1
OUT
SCI channel 1 serial
transmission
transmission
Service connector
UART serial output
61
P32
SDA
ODN
General port 32
EEPROM control
12CBUS data line
62
RXD1
RXD1
IN
SCI channel 1 serial reception
Service connector
UART input
63
P34
SCL
ODN
General port 34
EEPROM control
12CBUS clock line
64
P35
/FROMUP
IN
General port 35
Service connector
0: Service mode
65
VSS
POW
Ground pin
66
/DREQ0
/DREQ0
IN
DMAC channel 0 external
request
request
Mirror and SPF motor
acceleration/reduction control
acceleration/reduction control
0: Request effective
67
VSS
POW
Ground pin
68
VSS
POW
Ground pin
69
/CS5
—
OUT
Area 5 chip select
Reservation
L: Select
70
/DREQ1
/DREQ1
IN
DMAC channel 1 external
request
request
Lifter and separator motor
acceleration/reduction control
acceleration/reduction control
0: Request effective
71
P63
POFFR
OUT
General port 63
Power off relay control
H: AC switch OFF
72
P27
/ESPAGE
IN
General port 27
ERDH option page signal
detection
detection
0: Page effective
73
P26
/PCLPAGE
IN
General port 26
PCl operation page signal
detection
detection
0: Page effective
(Pin descriptions) IN: Input pin OUT: Output pin BIDIR: Bi-directional pin ODN: Open drain output pin TR1: 3-state output pin POW: Power pin
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Pin No.
Pin name
Signal name
I/O
Function
Purpose
Descriptions
74
P25
/FAXPAGE
IN
General port 25
FAX option page signal
detection
detection
0: Page effective
75
P24
/READY
OUT
General port 24
Machine ready signal
L: Machine ready state
76
P23
/PWOFF
OUT
General port 23
Power off signal
L: Power interruption
detecting state
detecting state
77
P22
/SCANSP
OUT
General port 22
Scan stop signal
L: Scanning operation
interruption
interruption
78
P21
/SCANST
OUT
General port 21
Scan start signal
L: Scanning operation
effective
effective
79
P20
/PRSTART
OUT
General port 20
Print start signal
L: Printing effective
80
/WDTOVR
—
OUT
Watch dog timer overflow
System reset
L: System restart
81
/RES
—
IN
System reset
System reset
0: Power on reset
82
NMI
—
IN
Non-maskable interruption
request
request
Reservation
1: Level fixing input
83
/STBY
—
IN
Stand-by
Reservation
1: Level fixing input
84
VCC
POW
Power pin
85
XTAL
—
IN
Oscillation pin
Oscillator (19.6608MHz)
86
EXTAL
—
OUT
Oscillation pin
Oscillator (19.6608MHz)
87
VSS
POW
Ground pin
88
â
CPUCLK
OUT
System clock
System clock
19.6608MHz clock output
89
VCC
POW
Power pin
90
/AS
/AS
OUT
Address strobe
System bus
L: Address effective
91
/RD
/RD
OUT
Lead strobe
System bus
L: Lead effective
92
/HWR
/HWR
OUT
Highlight enable
System bus
L: Highlight effective
93
/LWR
/LWR
OUT
Row write enable
System bus
L: Row write effective
94
PF2
/TMEN
OUT
General port F2
Toner motor drive control
L: Rotating
95
PF1
PMD
OUT
General port F1
Polygon motor drive control
H: Rotating
96
PF0
MMD
OUT
General port F0
Main motor drive control
H: Rotating
97
P50
/MMRDY
IN
General port 50
Main motor ready signal
0: Rotation stable state
98
P51
/PMRDY
IN
General port 51
Polygon motor ready signal
0: Rotation stable state
99
VSS
POW
Ground pin
100
VSS
POW
Ground pin
101
P52
/PRLINE
OUT
General port 52
Print line signal
L: Printing effective
102
P53
/SCLINE
OUT
General port 53
Scan line signal
L: Scanning operation
effective
effective
103
AVCC
POW
Analog power pin
104
VREF
POW
Analog reference pin
105
AN0
RTH
IN
Analog input 0
Fusing thermistor
temperature detection
temperature detection
106
AN1
—
IN
Analog input 1
Reservation
107
AN2
—
IN
Analog input 2
Reservation
108
AN3
TONER
IN
Analog input 3
Toner sensor
5V: Toner empty
109
AN4
—
IN
Analog input 4
Reservation
110
AN5
—
IN
Analog input 5
Reservation
111
DA0
DA0
OUT
Analog output 0
CCD reference + side
112
DA1
DA1
OUT
Analog output 1
CCD reference – side
113
AVSS
POW
Analog ground pin
114
VSS
POW
Ground pin
115
TCLKD
LFTCLK
IN
Timer clock external input
Separator motor step count
Separator motor clock input
116
TIOCA2
TMCLK
OUT
Timer clock external output
Toner motor clock
960Hz clock output
117
TCLKC
SFTCLK
IN
Timer clock external input
Shifter motor step count
Shifter motor clock input
118
TIOCA1
PMCLK
OUT
Timer clock external output
Polygon motor clock
2078.74Hz clock output
119
TCLKB
SPFCLK
IN
Timer clock external input
SPF motor step count
SPF motor clock input
120
TCLKA
MIRCLK
IN
Timer clock external input
Mirror motor step count
Mirror motor clock input
121
/DACK1
—
OUT
DMAC channel 1
acknowledge
acknowledge
Reservation
L: Acknowledge effective
122
/DACK0
—
OUT
DMAC channel 0
acknowledge
acknowledge
Reservation
L: Acknowledge effective
123
MD0
—
IN
Operation mode setting pin 0
Operation mode setting
(MODE 4)
(MODE 4)
Operation mode 4
(Pin descriptions) IN: Input pin OUT: Output pin BIDIR: Bi-directional pin ODN: Open drain output pin TR1: 3-state output pin POW: Power pin
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AR-160/161 FM/E [13] ELECTRICAL SECTION 12/1/1998
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Pin No.
Pin name
Signal name
I/O
Function
Purpose
Descriptions
124
MD1
—
IN
Operation mode setting pin 1
Operation mode setting
(MODE 4)
(MODE 4)
Operation mode 4
125
MD2
—
IN
Operation mode setting pin 2
Operation mode setting
(MODE 4)
(MODE 4)
Operation mode 4
126
PG0
RY/BY
IN
General port G0
Flash ROM busy signal
0: Busy state
127
/CS3
/CS3
OUT
Area 3 chip select
I/O extension ASIC chip select L: Select effective
128
/CS2
/CS2
OUT
Area 2 chip select
Image ASIC chip select
L: Select effective
(Pin descriptions) IN: Input pin OUT: Output pin BIDIR: Bi-directional pin ODN: Open drain output pin TR1: 3-state output pin POW: Power pin
(3) Image ASIC (HG73C039FD)
a. Outline
Fig. 4 shows the block diagram of the ASIC.
The ASIC is composed of the following three blocks; the image process section, the print control section, and the I/F section.
The image process section processes the image data from the CCD PWB according to the operation mode, such as shading, AE process,
resolution conversion. and zooming.
The print control section outputs the image-processed data during copying to the LSU (Laser unit) in synchronization with writing timing of the LSU.
The I/F section controls communication of interface (IEEE1284) with the host PC and controls DRAM of send/receive data buffer with the host PC.
(Only for models with the printer function)
The ASIC is controlled by the CPU which writes the operation mode and the set values necessary for each operation mode to the ASIC control
register.
The ASIC is composed of the following three blocks; the image process section, the print control section, and the I/F section.
The image process section processes the image data from the CCD PWB according to the operation mode, such as shading, AE process,
resolution conversion. and zooming.
The print control section outputs the image-processed data during copying to the LSU (Laser unit) in synchronization with writing timing of the LSU.
The I/F section controls communication of interface (IEEE1284) with the host PC and controls DRAM of send/receive data buffer with the host PC.
(Only for models with the printer function)
The ASIC is controlled by the CPU which writes the operation mode and the set values necessary for each operation mode to the ASIC control
register.
b. pin/signal table
PIN
No.
Signal name
IN/OUT
Description
1
/SCANSP
IN
Scanner process interrupt signal
2
/PRSTART
IN
Print start trigger signal
3
TMON
IN
Toner motor ON/OFF
4
TMCLK
IN
Toner motor reference clock
5
3.3V
Power
6
CPUAD7
IN
CPU address bus
7
CPUAD6
IN
8
GND
Power
9
CPUAD5
IN
CPU address bus
10
CPUAD4
IN
11
CPUAD3
IN
12
CPUAD2
IN
13
CPUAD1
IN
PIN
No.
Signal name
IN/OUT
Description
14
/CPUSYNC
OUT
Horizontal synchronization signal
15
/INTR
OUT
Interruption request signal
16
/CPUCS
IN
CPU chip select signal
17
/RESET
IN
Reset signal
18
5V
Power
19
GND
Power
20
3.3V
Power
21
GND
Power
22
MDATA15
IN/OUT
Data bus of DRAM (page memory)
23
MDATA14
IN/OUT
24
MDATA13
IN/OUT
25
MDATA12
IN/OUT
26
MDATA11
IN/OUT
AR-161
AR-160/161 FM/E [13] ELECTRICAL SECTION 12/1/1998
13 – 5
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