Sharp AL-1551 (serv.man4) Service Manual ▷ View online
AL-1551 ELECTRICAL SECTION 12-4
*
The signals which are hatched are added or revised to or from the
AL-1000.
93
/LWR
Output
Write Signal (Low Address)
94
SELIN3
Output
Input select 3
95
SELIN2
Output
Input select 2
96
SELIN1
Output
Input select 1
97
PR
Output
Power relay control PR
98
RRS
Output
Resist roller solenoid RPC
99
D-GND
100
D-GND
101
SCLK
Output
Clock Line for EEPROM
102
SDA
Output
Data Line for EEPROM
103
A5V
104
Analog Reference Voltage-A5V
105
RTH
Analog input Fusing Thermister
106
107
SIN1
Input
Sensor input 1
108
SIN2
Input
Sensor input 2
109
SIN3
Input
Sensor input 3
110
SIN4
Input
Sensor input 4
111
DAH
Analog
output
output
Reference Voltage (High) for CCD
112
DAL
Analog
output
output
Reference Voltage (Low) for CCD
113
AN-GND
114
D-GND
115
DMT-3
Motor output Duplex Motor Excitement
116
DMT-2
Motor output Duplex Motor Excitement
117
DMT-1
Motor output Duplex Motor Excitement
118
DMT-0
Motor output Duplex Motor Excitement
119
MRMT3
Motor output Mirror Motor Excitement
120
MRMT2
Motor output Mirror Motor Excitement
121
MRMT1
Motor output Mirror Motor Excitement
122
MRMT0
Motor output Mirror Motor Excitement
123
Input
CPU MODE SET <MODE 4> - GND
124
Input
CPU MODE SET <MODE 4> - GND
125
Input
CPU MODE SET <MODE 4> - Vcc
126
NC-pull up
127
DRST
Input
Drum reset detection
128
/CS2
Output
Chip Select for ASIC
PIN
No.
Signal
code
Input/output
Operating
( !"#$%&
AL-1551 ELECTRICAL SECTION 12-5
(2) ASIC (Signal table)
PIN No.
Signal name
IN/OUT
Connected to
Description
1
/SCANSP
IN
CPU (I/O)
Scanner process interrupt signal
2
/PRSTART
IN
CPU
Print start trigger signal
3
/TMEN
IN
CPU
Toner motor ON/OFF
4
TMCLK
IN
CPU
Toner motor reference clock
5
3.3V
Power
6
CPUAD7
IN
CPU
CPU address bus
7
CPUAD6
IN
CPU
CPU address bus
8
GND
Power
9
CPUAD5
IN
CPU
CPU address bus
10
CPUAD4
IN
CPU
CPU address bus
11
CPUAD3
IN
CPU
CPU address bus
12
CPUAD2
IN
CPU
CPU address bus
13
CPUAD1
IN
CPU
CPU address bus
14
/CPUSYNC
OUT
CPU
Horizontal synchronization signal
15
/ASICINT
OUT
CPU
Interruption request signal
16
/CS2
IN
CPU
CPU chip select signal
17
/RESET
IN
RESET IC
Reset signal
18
5V
Power
19
GND
Power
20
3.3V
Power
21
GND
Power
22
MDATA15
IN/OUT
DRAM
Data bus of DRAM (page memory)
23
MDATA14
IN/OUT
DRAM
Data bus of DRAM (page memory)
24
MDATA13
IN/OUT
DRAM
Data bus of DRAM (page memory)
25
MDATA12
IN/OUT
DRAM
Data bus of DRAM (page memory)
26
MDATA11
IN/OUT
DRAM
Data bus of DRAM (page memory)
27
MDATA10
IN/OUT
DRAM
Data bus of DRAM (page memory)
28
MDATA9
IN/OUT
DRAM
Data bus of DRAM (page memory)
29
MDATA8
IN/OUT
DRAM
Data bus of DRAM (page memory)
30
MDATA7
IN/OUT
DRAM
Data bus of DRAM (page memory)
31
3.3V
Power
32
MDATA6
IN/OUT
DRAM
Data bus of DRAM (page memory)
33
MDATA5
IN/OUT
DRAM
Data bus of DRAM (page memory)
34
GND
Power
35
MDATA4
IN/OUT
DRAM
Data bus of DRAM (page memory)
36
MDATA3
IN/OUT
DRAM
Data bus of DRAM (page memory)
37
MDATA2
IN/OUT
DRAM
Data bus of DRAM (page memory)
38
MDATA1
IN/OUT
DRAM
Data bus of DRAM (page memory)
39
MDATA0
IN/OUT
DRAM
Data bus of DRAM (page memory)
40
/RAS0
OUT
DRAM
RAS signal 0 of DRAM (page memory)
41
/RAS1
OUT
DRAM
RAS signal 1 of DRAM (page memory)
42
/RAS2
OUT
DRAM
RAS signal 2 of DRAM (page memory)
43
/RAS64
OUT
DRAM control (for panther) (Reserved)
44
3.3V
Power
45
/RAS16
OUT
DRAM control (for panther) (Reserved)
46
MAD0
OUT
DRAM
Address bus of DRAM (page memory)
47
GND
Power
48
MAD1
OUT
DRAM
Address bus of DRAM (page memory)
49
MAD2
OUT
DRAM
Address bus of DRAM (page memory)
50
MAD3
OUT
DRAM
Address bus of DRAM (page memory)
51
MAD4
OUT
DRAM
Address bus of DRAM (page memory)
52
MAD5
OUT
DRAM
Address bus of DRAM (page memory)
53
MAD6
OUT
DRAM
Address bus of DRAM (page memory)
54
MAD7
OUT
DRAM
Address bus of DRAM (page memory)
55
MAD8
OUT
DRAM
Address bus of DRAM (page memory)
56
MAD9
OUT
DRAM
Address bus of DRAM (page memory)
57
3.3V
Power
58
MAD10
OUT
DRAM
Address bus of DRAM (page memory)
) !"#$%&
AL-1551 ELECTRICAL SECTION 12-6
59
MAD11
OUT
DRAM
Address bus of DRAM (page memory)
60
GND
Power
61
/CAS0
OUT
DRAM
CAS signal of DRAM (page memory)
62
/CAS1
OUT
DRAM
CAS signal of DRAM (page memory)
63
/OE
OUT
DRAM
Read enable signal of DRAM (page memory)
64
/WE
OUT
DRAM
Write enable signal of DRAM (page memory)
65
OUTD0
OUT
Reserved
66
OUTD1
OUT
Reserved
67
OUTD2
OUT
Reserved
68
OUTD3
OUT
Reserved
69
3.3V
Power
70
OUTD4
OUT
Reserved
71
OUTD5
OUT
Reserved
72
GND
Power
73
OUTD6
OUT
Reserved
74
OUTD7
OUT
Reserved
75
OUTD8
OUT
Reserved
76
OUTD9
OUT
Reserved
77
OUTD10
OUT
Reserved
78
OUTD11
OUT
Reserved
79
OUTD12
OUT
Reserved
80
OUTD13
OUT
Reserved
81
OUTD14
OUT
Reserved
82
OUTD15
OUT
Reserved
83
/HSYNC
OUT
PCL board
Horizontal sync signal with print area output only
84
/PCLPRD
IN
PCL board
Print video data (serial) from PCL board
85
/PCLREQ
OUT
PCL board
DREQ signal to PCL board
86
/PCLACK
IN
PCL board
ACK signal from PCL board
87
/PCLCS
IN
PCL board
88
3.3V
Power
89
GND
Power
90
5V
Power
91
GND
Power
92
/FAXPRD
IN
Reserved
93
/FAXREQ
OUT
Reserved
94
/FAXACK
IN
Reserved
95
3.3V
Power
96
/FAXCS
IN
Reserved
97
/ESPRD
IN
Electric sort
board*(Reserved)
board*(Reserved)
(Reserved)
98
GND
Power
99
/ESREQ
OUT
Electric sort
board*(Reserved)
board*(Reserved)
(Reserved)
100
/ESACK
IN
Electric sort
board*(Reserved)
board*(Reserved)
(Reserved)
101
/ESCS
IN
Electric sort
board*(Reserved)
board*(Reserved)
(Reserved)
102
PARAD0
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
103
PARAD1
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
104
PARAD2
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
105
PARAD3
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
106
PARAD4
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
107
PARAD5
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
108
5V
Power
109
PARAD6
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
110
PARAD7
IN/OUT
1284 board connector
DATA bus (IEEE1284 communication port)
111
GND
Power
112
/REV
OUT
1284 board connector
ECP mode I/O select (LOW:P
→
H)
113
INIT
IN
1284 board connector
INIT signal (IEEE1284 communication port)
114
/SLCTIN
IN
1284 board connector
/SLCTIN signal (IEEE1284 communication port)
PIN No.
Signal name
IN/OUT
Connected to
Description
* !"#$%&
AL-1551 ELECTRICAL SECTION 12-7
115
/AUTOFD
IN
1284 board connector
/AUTOFD signal (IEEE1284 communication port)
116
/STB
IN
1284 board connector
/STB signal (IEEE1284 communication port)
117
/ACK
OUT
1284 board connector
/ACK signal (IEEE1284 communication port)
118
BUSY
OUT
1284 board connector
BUSY signal (IEEE1284 communication port)
119
PE
OUT
1284 board connector
PE signal (IEEE1284 communication port)
120
/FAULT
OUT
1284 board connector
/FAULT signal (IEEE1284 communication port)
121
5V
Power
122
SLCT
OUT
1284 board connector
/SLCTIN signal (IEEE1284 communication port)
123
/TESTPIN0
IN
TEST PIN
High: Normal Low: Test
124
GND
Power
125
PFCLK
IN
Tansmitter
Write clock
126
/TESTPIN1
IN
TEST PIN
High: Normal Low: Test
127
/SYNCEN
OUT
JITTER ADJUSTMENT IC Jitter adjustment IC trigger signal
128
SD10
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
129
SD11
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
130
SD12
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
131
SD13
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
132
SD14
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
133
5V Power
134
SD15
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
135
SD16
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
136
GND
Power
137
SD17
IN/OUT
SRAM (separation)
Data line to SRAM before are separation
138
SOE1
OUT
SRAM(separation)
Read enable line to SRAM before area separation
139
SWE1
OUT
SRAM(separation)
Write enable line to SRAM before area separation
140
SCS1
OUT
SRAM(separation)
Chip select line to SRAM before area separation
141
SOE0
OUT
SRAM(separation)
Read enable line to SRAM before area separation
142
SWE0
OUT
SRAM(separation)
Write enable line to SRAM before area separation
143
SCS0
OUT
SRAM(separation)
Chip select line to SRAM before area separation
144
SD00
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
145
SD01
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
146
5V
Power
147
SD02
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
148
SD03
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
149
GND
Power
150
SD04
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
151
SD05
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
152
SD06
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
153
SD07
IN/OUT
SRAM(separation)
Data line to SRAM before are separation
154
SAD0
OUT
SRAM(separation)
Address line to SRAM before area separation
155
SAD1
OUT
SRAM(separation)
Address line to SRAM before area separation
156
SAD2
OUT
SRAM(separation)
Address line to SRAM before area separation
157
SAD3
OUT
SRAM(separation)
Address line to SRAM before area separation
158
SAD4
OUT
SRAM(separation)
Address line to SRAM before area separation
159
SAD5
OUT
SRAM(separation)
Address line to SRAM before area separation
160
SAD6
OUT
SRAM(separation)
Address line to SRAM before area separation
161
SAD7
OUT
SRAM(separation)
Address line to SRAM before area separation
162
GND
Power
163
SAD8
OUT
SRAM(separation)
Address line to SRAM before area separation
164
SAD9
OUT
SRAM(separation)
Address line to SRAM before area separation
165
SAD10
OUT
SRAM(separation)
Address line to SRAM before area separation
166
SAD11
OUT
SRAM(separation)
Address line to SRAM before area separation
167
SAD12
OUT
SRAM(separation)
Address line to SRAM before area separation
168
SAD13
OUT
SRAM(separation)
Address line to SRAM before area separation
169
/f1
OUT
CCD PWB
CCD drive signal transfer clock (First phase)
170
/f2
OUT
CCD PWB
CCD drive signal transfer clock (Second phase)
171
/SH
OUT
CCD PWB
CCD drive signal shift pulse
172
5V Power
173
RS
OUT
CCD PWB
CCD drive signal reset pulse
PIN No.
Signal name
IN/OUT
Connected to
Description
+ !"#$%&
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