Sharp AL-1217 (serv.man17) Service Manual ▷ View online
AL-1226 ELECTRICAL SECTION 12 - 12
(1) Noise filter circuit
The filter circuit is composed of L and C. It reduces common noises
and normal mode noises generated from the AC line.
and normal mode noises generated from the AC line.
The common noise means that generated in each line for GND. Its
noise component is delivered through C001, C003, and C007 to GND.
noise component is delivered through C001, C003, and C007 to GND.
The normal noise means that overlapped in the AC line or the output
line. It is attenuated by C002, L001, C006, and L002. Refer to fig (2).
line. It is attenuated by C002, L001, C006, and L002. Refer to fig (2).
fig (2) Noise filter circuit
(2) Rush current prevention circuit and rectifying/
smoothing circuit
fig (3) Rush current prevention, rectifying/smoothing circuit
Since the AC power is directly rectified, if there were not this rush cur-
rent prevention resistor (TH001), an extremely large rush current
would flow due to a charging current flowing through the smoothing
capacitor C010 when turning on the power.
rent prevention resistor (TH001), an extremely large rush current
would flow due to a charging current flowing through the smoothing
capacitor C010 when turning on the power.
To prevent against this, the rush current prevention resistor TH001 is
provided between the rectifying diode D002 and the smoothing diode
C010, suppressing a rush current.
provided between the rectifying diode D002 and the smoothing diode
C010, suppressing a rush current.
The rectifying/smoothing circuit rectifies a 50/60Hz AC voltage with the
rectifying circuit, and smoothes it with the smoothing capacitor C010.
rectifying circuit, and smoothes it with the smoothing capacitor C010.
(3) Inverter and control circuit (Flyback converter system)
fig (4) Inverter and control circuit
This circuit is one-stone separate excitation DC-DC converter called
flyback converter, as shown in fig (4).
flyback converter, as shown in fig (4).
When an electromotive voltage of IC is applied through D012, R005,
and R006 to IC002, IC002 oscillates to conduct Q001.
and R006 to IC002, IC002 oscillates to conduct Q001.
As a result, a voltage is applied to the primary winding of the converter
transformer (T001) and at the same time a voltage is generated in the
driving winding of IC002 to operate IC002. Then IC002 turns ON/OFF
Q001 at the frequency of about 70KHz determined by R016.
transformer (T001) and at the same time a voltage is generated in the
driving winding of IC002 to operate IC002. Then IC002 turns ON/OFF
Q001 at the frequency of about 70KHz determined by R016.
Under the ON state, the voltage in the secondary winding is reversed
to the diode D103 and no current flows through the secondary winding
of T001.
to the diode D103 and no current flows through the secondary winding
of T001.
Under the OFF state, the current flowing through the primary winding is
in the same direction as the primary winding, conducting D103 and
transmitting energy to the secondary winding. Refer to fig (4).
in the same direction as the primary winding, conducting D103 and
transmitting energy to the secondary winding. Refer to fig (4).
fig (5) Operation waveform of the flyback converter
T001
D103
R109
R111
PC002
IC102
Q001
R012
R006
R005
R013
C013
R012
AC
8
7
6
IC002
R016
5
1
2
3 4
PC002
C010
secondary
winding
voltage
winding
voltage
AL-1226 ELECTRICAL SECTION 12 - 13
The control circuit is subject to negative feedback from the secondary
side as shown in fig (4). A photo coupler (PC002) is employed to insu-
late between the primary side and the secondary side to feed back the
control signal to the primary side.
side as shown in fig (4). A photo coupler (PC002) is employed to insu-
late between the primary side and the secondary side to feed back the
control signal to the primary side.
When the output voltage is increased by energy transmission from
T001, the voltage detected by R109 and R111 is compared with the
reference voltage of IC102. When it exceeds the reference voltage, the
current flowing through IC102 (that is, the photo diode current of
PC002) is increased and transmitted to the primary side. Then the
potential at the feedback pin (2 pin) of IC102 is decreased to control
Q001. Therefore, the change in the output voltage on the secondary
side is passed through IC102 and PC002 to control Q001, stabilizing
the output voltage.
T001, the voltage detected by R109 and R111 is compared with the
reference voltage of IC102. When it exceeds the reference voltage, the
current flowing through IC102 (that is, the photo diode current of
PC002) is increased and transmitted to the primary side. Then the
potential at the feedback pin (2 pin) of IC102 is decreased to control
Q001. Therefore, the change in the output voltage on the secondary
side is passed through IC102 and PC002 to control Q001, stabilizing
the output voltage.
(4) Overcurrent protection circuit (Primary side)
The inverter circuit of the primary side is connected with the current
detection resistor R102. When an overcurrent occurs in the secondary
side, the current flowing through the primary side inverter Q001 is
increased. The current is detected by R012, and passed through R013
to IC701 overcurrent restricting pin (3 pin) to turn OFF Q002, shutting
off all power. To resupply the power, turn off and on the power. Refer
to fig (4).
detection resistor R102. When an overcurrent occurs in the secondary
side, the current flowing through the primary side inverter Q001 is
increased. The current is detected by R012, and passed through R013
to IC701 overcurrent restricting pin (3 pin) to turn OFF Q002, shutting
off all power. To resupply the power, turn off and on the power. Refer
to fig (4).
(5) Rectifying/smoothing circuit (+5V)
fig (6) Rectifying/smoothing circuit
The high frequency pulse generated by the inverter circuit is
decreased by the converter transformer, rectified by the high frequency
diode D103, and smoothed by C103 and C104.
decreased by the converter transformer, rectified by the high frequency
diode D103, and smoothed by C103 and C104.
fig (7) +5V rectifying/smoothing circuit voltage waveform
Voltage waveform
Voltage waveform
AL-1226 CIRCUIT DIAGRAM 13 - 1
[13] CIRCUIT DIAGRAM
A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
MCU PWB (CPU SECTION)
1.
MCU PWB
C126 47p
1
2
BR116 33J
1 2 3 4
8 7 6 5
R107
*4 2
1
BR119 33J
1 2 3 4
8 7 6 5
BR122
33J
1
2
3
4
8
7
6
5
BR125
33J
1
2
3
4
8
7
6
5
R103
*1
2
1
X101
HC-49U/S
19.6608MHz
1
2
R108
10kJ
2
1
BR124
33J
1
2
3
4
8
7
6
5
R114 11kF
2
1
BR118 33J
1 2 3 4
8 7 6 5
R104
*3
2
1
R102
*2 2
1
BR123
33J
1
2
3
4
8
7
6
5
BR120 33J
1 2 3 4
8 7 6 5
R106
0J
2
1
C104 100p
1
2
C106
12p
1
2
C114
0.1u
1
2
C115
0.1u
1
2
C111
0.1u
1
2
C122
OPEN
1
2
C119
OPEN
1
2
C105 100p
1
2
C109
10u/16V
1
2
+
C112
0.1u
1
2
C120
OPEN
1
2
C124 0.1u
1
2
C110
0.1u
1
2
C117
OPEN
1
2
C113
0.1u
1
2
C103
*5
1
2
R109
OPEN
2
1
C125 22000p
1
2
C123
OPEN
1
2
C102
*6
1
2
R117 10kF
2
1
C108
0.1u
1
2
C121
OPEN
1
2
R105
0J
2
1
C118
OPEN
1
2
R112
10kJ
2
1
BR114
10kJ
1
2
3
4
8
7
6
5
L101
ZJSR5101-223
1
2
3
BR108
10kJ
1 2 3
4
8 7 6 5
BR115
10kJ
1 2 3 4
8 7 6 5
BR107
10kJ
1 2 3 4
8 7 6 5
BR110
10kJ
1 2 3 4
8 7 6 5
C128
0.1u
1
2
R111
10kJ
2
1
BR117
10kJ
1
2
3
4
8
7
6
5
BR109
10kJ
1 2 3 4
8 7 6 5
BR105
10kJ
1 2 3 4
8 7 6 5
BR101
10kJ
1
2
3
4
8
7
6
5
R101
OPEN
2
1
IC102
24WC02 or HT24LC02
E0
1
E1
2
E2
3
VSS
4
SD
A
5
SCL
6
WC
7
VCC
8
BR102
10kJ
1
2
3
4
8
7
6
5
BR103
10kJ
1
2
3
4
8
7
6
5
BR106
10kJ
1 2 3 4
8 7 6 5
BR104
10kJ
1 2 3 4
8 7 6 5
IC101
P2010/PLL701-01
Xin
1
Xout
2
FS0
3
Vss
4
SSon
5
MODOUT
6
SR0
7
VDD
8
BR112
10kJ
1
2
3
3
4
8
7
6
6
5
R271 10kJ
2
1
IC103
H8S/2320
HD6412320VF25(H8S/2320)
P35/SCK1
64
P34/SCK0
63
P33/RxD1
62
P32/RxD0
61
P31/TxD1
60
P30/TxD0
59
VCC
58
PD7/D15
57
PD6/D14
56
PD5/D13
55
PD4/D12
54
Vss
53
PD3/D11
52
PD2/D10
51
PD1/D9
50
PD0/D8
49
PE7/D7
48
PE6/D6
47
PE5/D5
46
PE4/D4
45
Vss
44
PE3/D3
43
PE2/D2
42
PE1/D1
41
PE0/D0
40
VCC
39
AV
c
c
103
Vref
104
P40/AN0
105
P41/AN1
106
P42/AN2
107
P43/AN3
108
P44/AN4
109
P45/AN5
110
P46/AN6/D
A
0
111
P47/AN7/D
A
1
112
AV
s
s
113
Vss
114
P17/PO15/TIOCB2/TCLKD
115
P16/PO14/TIOCA2
116
P15/PO13/TIOCB1/TCLKC
117
P14/PO12/TIOCA1
118
P13/PO11/TIOCD0/TCLKB
119
P12/PO10/TIOCC0/TCLKA
120
P11/PO9/TIOCB0/
D
A
CK1
121
P10/PO8/TIOCA0/
D
A
CK0
122
MD0
123
MD1
124
MD2
125
PG0/
CAS
126
PG1/
CS3
127
PG2/
CS2
128
PG3/CS1
1
PG4/CS0
2
Vss
3
NC
4
VCC
5
PC0/A0
6
PC1/A1
7
PC2/A2
8
PC3/A3
9
Vss
10
PC4/A4
11
PC5/A5
12
PC6/A6
13
PC7/A7
14
PB0/A8
15
PB1/A9
16
PB2/A10
17
PB3/A11
18
Vss
19
PB4/A12
20
PB5/A13
21
PB6/A14
22
PB7/A15
23
P A0/A16
24
P A1/A17
25
P A2/A18
26
P A3/A19
27
Vss
28
P A4/A20/
IRQ4
29
P A5/A21/
IRQ5
30
P A6/A22/
IRQ6
31
P A7/A23/
IRQ7
32
P67/
/
CS7IRQ3
33
P66/
/
CS6IRQ2
34
Vss
35
Vss
36
P65/IRQ1
37
P64/IRQ0
38
P53/ADTRG
102
P52/SCK2
101
Vss
100
Vss
99
P51/RxD2
98
P50/TxD2
97
PF0/BREQ
96
PF1/BA
CK
95
PF2/
/ WA
IT/BREQO
LCAS
94
PF3/LW
R
93
PF4/HWR
92
PF5/RD
91
PF6/AS
90
VCC
89
PF7/0
88
Vss
87
EXT AL
86
XT AL
85
VCC
84
STBY
83
NMI
82
RES
81
WDTO
VF
80
P20/PO0/TIOCA3
79
P21/PO1/YICOB3
78
P22/PO2/TIOCC3
77
P23/PO3/TIOCD3
76
P24/PO4/TIOCA4
75
P25/PO5/TIOCB4
74
P26/PO6/TIOCA5
73
P27/PO7/TIOCB5
72
P63/TEND1
71
P62/DREQ1
70
P61/
/
TEND0CS5
69
Vss
68
Vss
67
P60/
/
DREQ0CS4
66
Vss
65
BR121
33J
1
2
3
4
8
7
6
5
IC104
M51957BFP
NC
8
GND
4
VCC
7
NC
1
IN
2
NC
3
Cd
5
OUT
6
C107 0.1u
1
2
C101
0.1u
1
2
R270
OPEN
2
1
R115
10kJ
2
1
R118 10kJ
2
1
R116
OPEN
2
1
R276
33J
2
1
BR111
10kJ
1
2
3
4
8
7
6
5
R277
33J
2
1
R278
100J
2
1
R283
10kJ
2
1
R284 10kJ
2
1
R285
33J
2
1
R291
1kJ
2
1
D5
CPUCLK(NC)
D0
SPMT1
R
Y/BY
CCD_TG
D7
LW
R
D12
/CS0
/CS2
RESETOUT
D4
LW
R
D8
D15
/CS2
/SCANSP
/TRANSST
D10
/CS0
D3
MT_HOME
(FW)
D7
SCL
/CS1
F
AXSTS(NC)
/SCANST
/PRINTST
D6
CPU_SYNC
/PRINTST
D13
MT_HOME
D5
D0
CCD_TG
ARB_INT
SD
A
D12
CPUNRST
D9
SPMT0
D11
SPMT2
/SCANSP
D10
(FW)
SPMT3
CPUCLK(NC)
F
A
XSTS(NC)
D4
D2
/TRANSST
CPU_SYNC
D1
D9
SCL
D2
ARB_INT
D14
SPMT1
SPMT3
/CS1
SD
A
D3
F
AXCMD(NC)
A20
D6
D14
/SCANST
D8
D1
D15
SPMT0
SPMT2
F
A
XCMD(NC)
D13
D11
RY
/B
Y
A0
A5
A2
A4
A11
A19
A13
A3
A8
A10
A7
A12
A16
A14
A18
A1
A15
A17
A6
A9
A20
CPUNRST
RESET
OUT
HWR
HWR
RD
RD
RESET
OUT1
RESET
OUT1
VCC3
VCC3
CPU3.3
CPU3.3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
/ASIC_RST
A[19..0]
mt_at_home
(SIN1)
R
Y/BY
RT
H
SD
A
TMCLK
(PSW)
/CS0
/CS2
POFF
DMT3
SPMT1
DMT0
DMT2
/SCANST
SELIN1
SELIN3
CCD_TG
/PRINTST
CPU_SYNC
ARB_INT
SCL
(SIN3)
(KIN1)
D[15..0]
(SIN2)
PSL
(USBIN)
TMEN
(KIN2)
SPMT0
/CS1
PMCLK
SPMT2/MIRCNT
DMT1
/SCANSP
/TRANSST
(SPPD)
SPMT3
SELIN2
(FW)
/L
WR
TxD1
/RD
/HWR
ONL
D_CONT
BEO
CPUNRST
/CL_RESET
Spreading Range :
+/- 1.25%
R104(*3)
OPEN
0J
R103(*1)
OPEN
680J
R107(*4)
22J
OPEN
R102(*2)
0J
OPEN
C103(*5)
C102(*6)
22pF
22pF
15pF
15pF
*R102,R103,C102, and C103 are temtativ
e
(3-A2)
(2-A2)
(2-A2)
(3-A2)
(4-C3) (4-C3) (4-C3)
(9-B1) (9-B1)
(5-E3)
(4-D3)
(4-D3) (4-D3)
(2-A2) (2-A2)
(2-A2)
(2-A2)
(4-C2) (4-C2) (4-C2) (4-C2)
(8-C3)
(8-D3)
(2-A1)
(3-A2)
(3-C2)
(2-D1)
(2-A1)
(3-A3)
(2-A1)
(4-D4)
(8-C2)
(7-E1)
(2-A1)
(2-B4)
(7-E1)
(2-A2)
(3-A1)
(6-D3) (6-D3) (6-D4) (6-D4) (5-B2) (5-B1) (2-A2) (2-A2) (4-D4) (4-D4) (3-B2)
(9-B1)
(2-D1)
(9-B3)
(8-A2)
(8-C4)
CPU por
t selection of a /ASIC_RST output
PF6
33J mounted on R116 and R285 are OPEN
P34
33J mounted on R285 and R116 are OPEN
(8-C1)
(3-B2)
When IC101 is
,
m
ounted
NO
T mounted
1/9
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